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    Apparatus and method for high-voltage transient blocking using low voltage elements
    61.
    发明授权
    Apparatus and method for high-voltage transient blocking using low voltage elements 有权
    使用低电压元件的高压瞬态阻塞的装置和方法

    公开(公告)号：US07646576B2

    公开(公告)日：2010-01-12

    申请号：US11271059

    申请日：2005-11-09

    Applicant: Richard A. Harris ,  Francois Hebert

    Inventor： Richard A. Harris ,  Francois Hebert

    IPC: H02H3/20 ,  H02H9/04

    CPC classification number: H02H9/025 ,  H01L27/0266 ,  H01L27/0727 ,  H01L29/808 ,  H02H9/046

    Abstract: An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.

    Abstract translation: 一种用于使用具有与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）的装置和方法，使得瞬态改变偏置电压Vp p沟道器件和n沟道器件的偏置电压Vn一致。 具体地，改变偏置电压，使得p沟道器件和n沟道器件相互切断以阻止瞬变。 耗尽型n沟道器件采用一组级联的低压耗尽型场效应晶体管（FET），例如连接源极到漏极的金属氧化物 - 硅场效应晶体管（MOSFET），以实现所需的高电压工作 的TBU。

    Bottom source LDMOSFET structure and method
    62.
    发明申请
    Bottom source LDMOSFET structure and method 有权
    底源LDMOSFET结构和方法

    公开(公告)号：US20090263947A1

    公开(公告)日：2009-10-22

    申请号：US12456949

    申请日：2009-06-25

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L21/336

    CPC classification number: H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: This invention discloses a method to form a bottom-source lateral diffusion MOS (BS-LDMOS) device with a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The method includes a step of applying a sinker-channel mask for carrying out a deep sinker multiple energy implant to form a combined sinker-channel region in lower portion of an epitaxial layer to function as a buried source-body contact extending to and contacting a bottom of the substrate functioning as a bottom source electrode.

    Abstract translation: 本发明公开了一种形成底源横向扩散MOS（BS-LDMOS）器件的方法，源极区域设置在半导体衬底的顶表面附近的漏极区域的横向相对的位置，该半导体衬底在源极区域和漏极区域之间支撑栅极 。 该方法包括以下步骤：施加沉降通道掩模，用于进行深沉沉多次能量注入，以在外延层的下部形成组合沉降沟道区，以用作延伸到和接触的外部源体接触 底部的底部用作底部源极。

    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
    63.
    发明申请
    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
    自对准开槽积分型场效应晶体管（AccuFET）结构及方法

    公开(公告)号：US20090218619A1

    公开(公告)日：2009-09-03

    申请号：US12074280

    申请日：2008-03-02

    Applicant: Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    Inventor： Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    IPC: H01L29/739 ,  H01L21/3205

    CPC classification number: H01L29/7828 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666

    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

    Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。

    Planar split-gate high-performance MOSFET structure and manufacturing method
    64.
    发明申请
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US20090181503A1

    公开(公告)日：2009-07-16

    申请号：US12381813

    申请日：2009-03-16

    Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC: H01L21/337

    CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    Abstract translation: 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

    Planar split-gate high-performance MOSFET structure and manufacturing method
    69.
    发明申请
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US20070278571A1

    公开(公告)日：2007-12-06

    申请号：US11444853

    申请日：2006-05-31

    Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC: H01L29/94 ,  H01L29/76

    CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    Abstract translation: 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

    Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures
    70.
    发明申请
    Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures 审中-公开
    增加具有垂直串联电容结构的半导体器件中的击穿电压

    公开(公告)号：US20060255401A1

    公开(公告)日：2006-11-16

    申请号：US11202523

    申请日：2005-08-11

    Applicant: Robert Yang ,  Francois Hebert

    Inventor： Robert Yang ,  Francois Hebert

    IPC: H01L29/76 ,  H01L29/94

    CPC classification number: H01L29/7802 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/861

    Abstract: This invention relates to an apparatus and method for achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. The capacitive property of the intermediate region is established by an appropriately chosen material constitution and is further controlled by a predetermined constitution of the insulating trench. The apparatus and method of invention are useful in any number of semiconductor devices including, among other, transistors, bipolar transistors, MOSFETs, JFETs, thyristors and diodes.

    Abstract translation: 本发明涉及一种用于实现半导体器件中的高击穿电压和低导通电阻的装置和方法，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部，中间和底部区域。 该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。 具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质 区域，使得击穿电压V BAT最大化，导通电阻最小化。 通过适当选择的材料结构建立中间区域的电容性质，并通过绝缘沟槽的预定结构进一步控制。 本发明的装置和方法可用于任何数量的半导体器件，其中包括晶体管，双极晶体管，MOSFET，JFET，晶闸管和二极管。

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