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    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
    64.
    发明授权
    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
    毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物

    公开(公告)号：US08900954B2

    公开(公告)日：2014-12-02

    申请号：US13289051

    申请日：2011-11-04

    Applicant: James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    Inventor： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC: H01L29/772 ,  H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

    Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

    Abstract translation: 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

    TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR
    66.
    发明申请
    TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
    具有用于减少基极集电极结电容的窄层内基板收集器区域的晶体管和形成晶体管的方法

    公开(公告)号：US20130214275A1

    公开(公告)日：2013-08-22

    申请号：US13401064

    申请日：2012-02-21

    Applicant: James W. Adkisson ,  David L. Harame ,  Qizhi Liu

    Inventor： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

    IPC: H01L29/737 ,  H01L21/331

    CPC classification number: H01L29/732 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

    Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

    Abstract translation: 公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。 晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。 相对薄的种子层覆盖沟槽隔离区域和收集器区域。 该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。 本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。 非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

    Methods of forming silicide strapping in imager transfer gate device
    69.
    发明授权
    Methods of forming silicide strapping in imager transfer gate device 有权
    在成像器传输门装置中形成硅化物带的方法

    公开(公告)号：US08158453B2

    公开(公告)日：2012-04-17

    申请号：US12699419

    申请日：2010-02-03

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L21/336

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

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