公开(公告)号：US20110140185A1

公开(公告)日：2011-06-16

申请号：US13032009

申请日：2011-02-22

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近，在这些端子处，凸起电极 （208）。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US20070241330A1

公开(公告)日：2007-10-18

申请号：US11808808

申请日：2007-06-13

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07247879B2

公开(公告)日：2007-07-24

申请号：US10873360

申请日：2004-06-23

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L29/04

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07138722B2

公开(公告)日：2006-11-21

申请号：US11057495

申请日：2005-02-15

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US20060125116A1

公开(公告)日：2006-06-15

申请号：US11350919

申请日：2006-02-10

申请人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

发明人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC分类号： H01L23/48

CPC分类号： H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

摘要翻译： 多芯片模块具有至少两个半导体芯片。 每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层 土地和半导体芯片。 半导体芯片通过外部端子放置在安装板上。 位于所述第二半导体芯片的最外端部的最外侧端子之间的距离小于第一半导体芯片的距离。

公开(公告)号：US07057283B2

公开(公告)日：2006-06-06

申请号：US10825436

申请日：2004-04-16

申请人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

发明人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/3157 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3114 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06102 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2924/01034

摘要： A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide α-ray shielding of the semiconductor device.

摘要翻译： 一种半导体装置，其中可以在没有任何底部填充的情况下进行倒装芯片接合，并且其包括半导体器件，通过掩模印刷含有颗粒的电绝缘材料在半导体器件上形成的电绝缘层，以及形成在电学上的外部连接端子 绝缘层并与半导体器件的电极电连接。 电绝缘层形成为具有提供半导体器件的α射线屏蔽的厚度。

公开(公告)号：US07013564B2

公开(公告)日：2006-03-21

申请号：US09971566

申请日：2001-10-09

申请人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

发明人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

IPC分类号： H01R43/00 ,  H05K13/00

CPC分类号： H05K1/181 ,  B23K1/0016 ,  B23K35/004 ,  B23K35/007 ,  B23K35/262 ,  B23K2101/40 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/532 ,  H01L24/29 ,  H01L2224/83101 ,  H01L2924/01322 ,  H01L2924/15747 ,  H05K3/3426 ,  H05K3/3463 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T428/12708 ,  Y10T428/12715 ,  H01L2924/00

摘要： A method of producing an electronic device by connecting a lead of a semiconductor device with an electrode of a circuit board to form a bonded structure. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

摘要翻译： 一种通过将半导体器件的引线与电路板的电极连接以形成接合结构来制造电子器件的方法。 在接合结构中，通过Sn-Bi合金层将无铅Sn-Ag-Bi合金焊料施加到电极。 Sn-Bi合金优选含有1〜20重量％的Bi，以获得良好的焊料润湿性。 为了获得本发明中具有较高可靠性的理想的接合特性，在Sn-Bi合金层下方设置有铜层，从而获得足够的接合强度。

公开(公告)号：US20050245061A1

公开(公告)日：2005-11-03

申请号：US11168460

申请日：2005-06-29

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L23/29 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L21/50

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

摘要翻译： 本发明是一种具有半导体元件的半导体器件，该半导体器件通过沿着划线在一侧形成电极焊盘切割半导体晶片而获得，半导体元件保护层在半导体元件上具有在该焊盘上的开口，应力缓冲 在该焊盘上具有开口的层上的引线部分，经由开口从电极焊盘到达层的引线部分，引线部分上的外部电极和层上的导体保护层，层和导体保护层 层，形成在划线内的半导体元件的端面上的各个端面，并露出从端面的端面到划线的内侧的范围。

公开(公告)号：US06949416B2

公开(公告)日：2005-09-27

申请号：US10765916

申请日：2004-01-29

申请人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Yoshihide Yamaguchi

发明人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Yoshihide Yamaguchi

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/12 ,  H01L23/31 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L23/3114 ,  H01L27/10814 ,  H01L27/10897 ,  H01L2224/0392 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05171

摘要： Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

摘要翻译： 公开了一种能够提高晶片级CSP中的重新布线层的布局自由度的技术，其中通过切割熔丝进行缺陷修复。 更具体地，在通过将激光束照射到熔丝进行缺陷修复之后，将有机钝化层（光敏聚酰亚胺层）填充在保险丝开口中。 此后，在有机钝化层上形成重路由层，凸起焊盘，最上布线层和焊料凸块。 在缺陷修复的以下步骤中，在低于260℃的温度下进行固化弹性体层和最上层保护层的烘烤过程，以防止存储单元的更新时间的变化。

公开(公告)号：US06822317B1

公开(公告)日：2004-11-23

申请号：US09698168

申请日：2000-10-30

申请人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

发明人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

IPC分类号： H01L23495

CPC分类号： H01L23/3114 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3157 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01034

摘要： A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.

摘要翻译： 一种半导体器件，包括半导体器件，形成在半导体器件上的电绝缘层和形成在电绝缘层上并与半导体器件的电极电连接的外部连接端子，其中电源/接地线和信号线 在从电绝缘层的边缘到电绝缘层的均匀厚度平坦部分的区域中，布线图案的种类不同。