公开(公告)号：US20230307251A1

公开(公告)日：2023-09-28

申请号：US18324686

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2225/06568

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US11769731B2

公开(公告)日：2023-09-26

申请号：US17229322

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/818 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US11764139B2

公开(公告)日：2023-09-19

申请号：US17372747

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/01047 ,  H01L2224/05611 ,  H01L2924/01082 ,  H01L2224/81121 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/1144 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

公开(公告)号：US11749626B2

公开(公告)日：2023-09-05

申请号：US17222249

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01P3/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01L23/31 ,  H01Q9/04 ,  H01L21/683 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01P3/003 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/0457 ,  H01L21/486 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3025 ,  H01Q21/065

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US20230274976A1

公开(公告)日：2023-08-31

申请号：US18302545

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/76871 ,  H01L21/32139 ,  H01L21/565 ,  H01L21/76856 ,  H01L23/3107 ,  H01L23/53238 ,  H01L24/09 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L23/5226 ,  H01L2224/02379

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

公开(公告)号：US20230253369A1

公开(公告)日：2023-08-10

申请号：US18302496

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L24/97 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L21/563 ,  H01L21/78 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L23/3128

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US11721559B2

公开(公告)日：2023-08-08

申请号：US17664458

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20230230962A1

公开(公告)日：2023-07-20

申请号：US18190341

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/81 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/81007 ,  H01L2224/81801 ,  H01L2224/81948 ,  H01L2224/81947 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/13147 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/05571 ,  H01L2924/381 ,  H01L2224/13101 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16145 ,  H01L2224/81141 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2224/05558

Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

公开(公告)号：US20230230882A1

公开(公告)日：2023-07-20

申请号：US17721109

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Yi-Chao Mao ,  Tsung-Fu Tsai ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/02076 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/08 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2223/5446 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments provide a precutting technique to cut parallel openings at a front surface of a device wafer, then flipping the device wafer over and completing the cut from the back side of the device wafer to singulate a die from the wafer. The precutting technique and back side cutting technique combined provides an indentation in the side surface(s) of the device.

公开(公告)号：US20230207478A1

公开(公告)日：2023-06-29

申请号：US18179083

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Yun Chen Hsieh ,  Chen-Hua Yu ,  Hui-Jung Tsai

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.