公开(公告)号：US06545855B1

公开(公告)日：2003-04-08

申请号：US10004554

申请日：2001-12-03

Applicant: Scott W. Repplinger ,  Jiri Slaby ,  Christopher J. Hoyle ,  Brian Lau

Inventor： Scott W. Repplinger ,  Jiri Slaby ,  Christopher J. Hoyle ,  Brian Lau

IPC: H01G220

CPC classification number: H01G2/065 ,  H01C1/01 ,  H01C1/14 ,  H05K1/0216 ,  H05K3/308 ,  H05K3/3426 ,  H05K2201/0792 ,  H05K2201/10015

Abstract: An apparatus (100) for reducing inductance in a capacitor having a first terminal (12) and a spaced-apart second terminal (14), includes a first conductive plate (120) and a second conductive plate (140). The first conductive plate (120) is electrically coupled to the first terminal (12). The second conductive plate (140) is electrically coupled to the second terminal (14) and is disposed in parallel with the first conductive plate (120) so as to overlap at least a portion of the first conductive plate (120). An insulating member (122 and 142) is disposed between the first conductive plate (120) and the second conductive plate (140). The insulating member (122 and 142) insulates the first conductive plate (120) from the second conductive plate (140).

Abstract translation: 一种用于减小具有第一端子（12）和间隔开的第二端子（14）的电容器中的电感的装置（100），包括第一导电板（120）和第二导电板（140）。 第一导电板（120）电耦合到第一端子（12）。 第二导电板（140）电耦合到第二端子（14）并且与第一导电板（120）平行设置，以便与第一导电板（120）的至少一部分重叠。 绝缘构件（122和142）设置在第一导电板（120）和第二导电板（140）之间。 绝缘构件（122和142）将第一导电板（120）与第二导电板（140）绝缘。

公开(公告)号：US20020156538A1

公开(公告)日：2002-10-24

申请号：US10127044

申请日：2002-04-19

Inventor： Nai-Shung Chang

IPC: G05B015/00 ,  G05B019/18 ,  G05B015/02 ,  G05B011/01

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/0216 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/094 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A data processing system including a control chip, a central processing unit and a printed circuit board is disclosed. The control chip has a substrate stack that includes, from top to bottom, a first signal layer, a first reference layer at a first reference voltage, a second reference layer at a second reference voltage and a second signal layer. The central processing unit has a substrate stack that includes, from top to bottom, a third signal layer, a third reference layer at the first reference voltage, a fourth reference layer at the second reference voltage and a fourth signal layer. The printed circuit board has a stack structure that includes, from top to bottom, a fifth signal layer, a fifth reference layer at the first reference voltage, a sixth reference layer at the second reference voltage and a sixth signal layer. The second signal layer of the control chip and the fourth signal layer of the central processing unit are adjacent to the fifth signal layer. Critical signals may be transmitted from the central processing unit to the control chip via the third signal layer, the fifth signal layer and the first signal layer under a better return path.

Abstract translation: 公开了一种包括控制芯片，中央处理单元和印刷电路板的数据处理系统。 控制芯片具有从顶部到底部包括第一信号层，第一参考电压的第一参考层，第二参考电压的第二参考层和第二信号层的衬底堆叠。 中央处理单元具有从顶部到底部包括第三信号层，第一参考电压的第三参考层，第二参考电压处的第四参考层和第四信号层的衬底堆叠。 印刷电路板具有从顶部到底部包括第五信号层，第一参考电压的第五参考层，第二参考电压处的第六参考层和第六信号层的堆叠结构。 控制芯片的第二信号层和中央处理单元的第四信号层与第五信号层相邻。 临界信号可以在更好的返回路径下经由第三信号层，第五信号层和第一信号层从中央处理单元发送到控制芯片。

公开(公告)号：US06400028B1

公开(公告)日：2002-06-04

申请号：US09119467

申请日：1998-07-20

Applicant: Edward Allyn Burton

Inventor： Edward Allyn Burton

IPC: H01L2940

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/114 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09854

Abstract: An improvement is presented for connecting conductive components of a built-up circuit board. Rather than using vias or micro vias to connect a conductive layer to a conductive component separated by an insulating layer, an elongated via is used. In one embodiment, the elongated via has a length that is sufficient to directly coupled a first layer to the edge of a via in a lower layer. Thus, it can be said that the elongated via “self-aligns” with the via in the lower layer. In doing so, electrical connections from one side of a circuit board to a component coupled to the other side of the circuit board are more direct leading to a reduction in parasitic induction.

Abstract translation: 提出了用于连接积层电路板的导电部件的改进。 不是使用通孔或微通孔将导电层连接到由绝缘层分离的导电部件，而是使用细长的通孔。 在一个实施例中，细长通孔具有足以将第一层直接耦合到下层中的通孔的边缘的长度。 因此，可以说细长通孔与下层中的通孔“自对准”。 在这样做时，从电路板的一侧到耦合到电路板的另一侧的部件的电连接更直接地导致寄生感应的减小。

公开(公告)号：US20020047092A1

公开(公告)日：2002-04-25

申请号：US09970550

申请日：2001-10-03

Inventor： Frank G. Mikalauskas

IPC: G01R023/02

CPC classification number: H05K1/0248 ,  G01R31/2853 ,  H05K1/0219 ,  H05K1/025 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/09727

Abstract: A discontinuity, such as a via, in a signal transmission line can introduce a parasitic element that affects the signal transmission. The method in accordance with the present invention is directed to counteracting the transmission line parasitic element discontinuity. The method includes determining the amount of parasitic capacitance or inductance that is introduced at a portion of the transmission line, such as by the via. A suitable amount of delay is introduced to the transmission line by way of correction impedance in order to counteract the affects of the parasitic element. The delay is calculated taking into account at least in part the correction impedance and the parasitic element effect. The correction impedance is suitably added to a portion of the transmission line at which the parasitic element is present.

Abstract translation: 在信号传输线路中的诸如通路的不连续性可以引入影响信号传输的寄生元件。 根据本发明的方法旨在抵消传输线寄生元件不连续性。 该方法包括例如通过通孔确定在传输线的一部分处引入的寄生电容或电感的量。 通过校正阻抗将适当的延迟量引入传输线，以抵消寄生元件的影响。 至少部分地考虑校正阻抗和寄生元件效应来计算延迟。 校正阻抗适当地添加到存在寄生元件的传输线的一部分。

公开(公告)号：US06232562B1

公开(公告)日：2001-05-15

申请号：US09406717

申请日：1999-09-28

Applicant: Kiichi Kikuchi ,  Yuji Ebinuma ,  Yasuo Hosaka ,  Yoshiyuki Wasada ,  Kenji Kaneta ,  Hajime Hasegawa ,  Mitsuaki Ootani

Inventor： Kiichi Kikuchi ,  Yuji Ebinuma ,  Yasuo Hosaka ,  Yoshiyuki Wasada ,  Kenji Kaneta ,  Hajime Hasegawa ,  Mitsuaki Ootani

IPC: H05K116

CPC classification number: H05K1/0218 ,  H05K1/181 ,  H05K2201/0715 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/1003 ,  Y02P70/611

Abstract: A hybrid integrated circuit device is provided which suppresses lowering of the inductance value of a mounted coil component. A hybrid integrated circuit device according to the present invention has such a structure that a wiring pattern is provided on at least one main face of a substrate, a laid core type coil component is mounted on at least one main surface of the substrate, and a conductor pattern including a ground pattern is provided at least either on a main face opposite to the surface of the substrate upon which the laid core type coil component is mounted or in an interior of the substrate. In particular, the hybrid integrated circuit device has a configuration such that a magnetic flux passing window, having an absence of ground pattern, is provided in an orthographic projection area corresponding to a winding portion of the coil component in the conductor pattern.

Abstract translation: 提供一种混合集成电路器件，其抑制安装的线圈部件的电感值的降低。 根据本发明的混合集成电路器件具有在基板的至少一个主面上设置布线图案的结构，在基板的至少一个主表面上安装铺设的芯型线圈部件， 在与放置的芯型线圈部件的基板的表面相反的主面上或者在基板的内部，至少提供包括接地图案的导体图案。 特别地，混合集成电路器件具有这样的结构，即在与导体图案中的线圈部件的绕组部分对应的正投影区域中设置不具有接地图案的磁通通过窗口。

公开(公告)号：US6107877A

公开(公告)日：2000-08-22

申请号：US288906

申请日：1999-04-09

Applicant: Philip Miguelez ,  Rudolph Menna ,  Shutong Zhou ,  Timothy Cope

Inventor： Philip Miguelez ,  Rudolph Menna ,  Shutong Zhou ,  Timothy Cope

IPC: H03F1/32 ,  H03F1/52 ,  H05K1/02 ,  H05K3/00 ,  H03F1/00 ,  H03F1/26

CPC classification number: H03F1/523 ,  H03F1/3276 ,  H05K1/0253 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K3/0061

Abstract: An in-line distortion generator is coupled to an RF amplifier on a single PC board for producing an output signal of useful amplitude but with low composite triple beat and cross modulation distortions. The backplane under the section of the PC board upon which the distortion circuit resides is removed and the portion of the heat sink under the removed portion of the backplane is also removed. This eliminates any parasitic capacitances that could degrade the performance of the RF amplifier, thereby making the distortion circuit transparent to the RF amplifier. Furthermore, the layout of the predistortion circuitry has been specifically designed to enhance the performance of the circuitry without inducing any negative operating characteristics on the associated RF amplifier.

Abstract translation: 在线失真发生器耦合到单个PC板上的RF放大器，用于产生有用幅度的输出信号，但具有低复合三重拍摄和交叉调制失真。 去除了失真电路所在的PC板部分下的背板，并且除去背板拆卸部分下方的散热器部分。 这消除了可能降低RF放大器性能的任何寄生电容，从而使失真电路对RF放大器是透明的。 此外，预失真电路的布局已经被专门设计用于增强电路的性能，而不会在相关RF放大器上引起任何负的工作特性。

公开(公告)号：US6081430A

公开(公告)日：2000-06-27

申请号：US072792

申请日：1998-05-05

Applicant: George Sterling La Rue

Inventor： George Sterling La Rue

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/32 ,  H05K3/36 ,  H05K7/14 ,  H01K12/16

CPC classification number: H05K1/025 ,  H05K1/141 ,  H05K7/1441 ,  H05K2201/0314 ,  H05K2201/044 ,  H05K2201/045 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2201/09845 ,  H05K2201/10689 ,  H05K3/325 ,  H05K3/366 ,  H05K3/368

Abstract: A backplane consisting of segmented bus lines on a mother board with loop-through connections to active transceivers mounted on connectors to daughter boards. The transceivers isolate the interconnect to the daughter boards from the bus lines. The loop-through transmission line on the connectors preserves the impedance of the bus lines and allows the interconnect stub to the transceivers to be short, minimizing reflections and enabling high-speed backplane operation. The connectors are removable from the motherboard for repair.

Abstract translation: 一个背板，由主板上的分段总线线路组成，其中连接到与子板连接器上的主动收发器。 收发器将母线的互连与子板隔离。 连接器上的环通传输线保留总线的阻抗，并允许收发器的互连短路短路，最小化反射并实现高速背板操作。 连接器可从主板上拆下进行维修。

公开(公告)号：US06021564A

公开(公告)日：2000-02-08

申请号：US159140

申请日：1998-09-23

Applicant: David A. Hanson

Inventor： David A. Hanson

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/11 ,  H01K3/10

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/66 ,  H05K1/115 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09627 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Abstract translation: 一种通过提供第一导电层在叠层基板中制造低电感导电通孔的方法。 在第一导电层上形成第一电介质层。 在第一电介质层上形成第二导电层。 第一导电路径形成在沿着第一节点和第二节点之间的第一路由延伸的第一导电层中。 第一导电盲通孔在第二节点处连接到第一导电路径，其中第一通孔形成在第二节点处的第一介电层中。 最后，在连接到第一盲通孔的第二导电层中形成第二导电路径。 第二导电路径沿着第二路径在第三节点和第一盲孔之间延伸。 第二路线与第一路线的至少一部分相同。

公开(公告)号：US5987337A

公开(公告)日：1999-11-16

申请号：US874479

申请日：1997-06-16

Applicant: Kei Takaya

Inventor： Kei Takaya

IPC: H01Q13/08 ,  H01M2/10 ,  H01M2/20 ,  H01Q1/22 ,  H04B1/08 ,  H04Q7/14 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01M2/02 ,  H04B1/38

CPC classification number: H05K1/0233 ,  H01M2/1044 ,  H01M2/20 ,  H04B1/086 ,  H05K1/18 ,  H05K2201/0792 ,  H05K2201/10037 ,  H05K2201/10446 ,  H05K3/3426

Abstract: A radio pager of the present invention includes battery terminals each having an inductance component. The pager therefore reduces the fall of antenna efficiency as far as possible without resorting to any extra part. In addition, a coin type battery is located in the vicinity of short bars included in the pager so as to prevent the antenna efficiency from decreasing.

Abstract translation: 本发明的无线寻呼机包括各自具有电感分量的电池端子。 因此，寻呼机尽可能地减少天线效率的下降，而不需要额外的部分。 此外，硬币型电池位于寻呼机中包括的短条附近，以防止天线效率降低。

公开(公告)号：US5519366A

公开(公告)日：1996-05-21

申请号：US252238

申请日：1994-06-01

Applicant: Toshimi Kaneko ,  Masahiko Kawaguchi ,  Katsuji Matsuta

Inventor： Toshimi Kaneko ,  Masahiko Kawaguchi ,  Katsuji Matsuta

IPC: H01P1/203 ,  H05K1/02 ,  H05K3/34 ,  H01P1/20

CPC classification number: H01P1/20381 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/0792 ,  H05K2201/09381 ,  H05K2201/1006 ,  H05K2201/10969 ,  H05K2201/2081 ,  Y02P70/613

Abstract: A strip line filter has at least two strip lines and a common ground electrode, and on an end, has a solder ground terminal electrode and at least two link ground terminal electrodes at a distance from the solder ground terminal electrode. The solder ground terminal electrode is electrically connected with the common ground electrode, and the link ground terminal electrodes electrically connect each of the strip lines with the common ground electrode. Another strip line filter has at least two strip lines and a common ground electrode, and on an end, has a ground terminal electrode which has a solder portion and at least two arm portions extending from the solder portion. The ground terminal electrode is electrically connected with the common ground electrode via the solder portion and with the strip lines via the arm portions.

Abstract translation: 带状线滤波器具有至少两条带状线和公共接地电极，并且其一端具有焊料接地端子电极和距离焊接接地端子电极一定距离的至少两个连接接地端子电极。 焊接接地端子电极与公共接地电极电连接，并且连接接地端子电极将每条带状线与​​公共接地电极电连接。 另一带状滤波器具有至少两条带状线和公共接地电极，一端具有接地端子电极，该接地端子电极具有焊接部分和至少两个从焊料部分延伸的臂部分。 接地端子电极经由焊料部分与公共接地电极电连接，并且经由臂部分与带状线电连接。