公开(公告)号：US20130087916A1

公开(公告)日：2013-04-11

申请号：US13270850

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC: H01L23/498 ,  H01L21/60 ,  H01L21/50

CPC classification number: H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

公开(公告)号：US20130075937A1

公开(公告)日：2013-03-28

申请号：US13246556

申请日：2011-09-27

Applicant: Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/28 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract translation: 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。

公开(公告)号：US20130049234A1

公开(公告)日：2013-02-28

申请号：US13216825

申请日：2011-08-24

Applicant: Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L23/28

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Abstract translation: 提供了一种用于将基底分离成单个模具的方法和装置，并且提供了所得到的结构。 在衬底内形成诸如非晶层的改性层。 可以使用聚焦在衬底内的激光来产生修饰层。 改性层产生比周围的基材更容易破裂的相对较弱的区域。 结果，衬底可以被拉开到分开的部分中，从而沿着修饰层裂开衬底。 在分离之前或之后，骰子或其它组分可附着于基底。

公开(公告)号：US08338945B2

公开(公告)日：2012-12-25

申请号：US12953130

申请日：2010-11-23

Applicant: Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81805

Abstract: Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

Abstract translation: 用于提供模制芯片插入件结构和组装的装置和方法。 提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。 具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。 在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。 公开了用于形成模制芯片内插器结构的方法。

公开(公告)号：US08247285B2

公开(公告)日：2012-08-21

申请号：US12341674

申请日：2008-12-22

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/7833

Abstract: A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1-xGex source/drain regions are doped in-situ during formation, x

Abstract translation: 提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。 该方法提供具有Ge沟道区的衬底。 在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。 牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。 凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

公开(公告)号：US20120145204A1

公开(公告)日：2012-06-14

申请号：US12964097

申请日：2010-12-09

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC: B08B3/08 ,  B08B3/02

CPC classification number: H01L21/67051 ,  H01L21/68728

Abstract: A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

Abstract translation: 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US20120112282A1

公开(公告)日：2012-05-10

申请号：US13351824

申请日：2012-01-17

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7833 ,  H01L21/02175 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

Abstract: Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the metal oxide layer are converted into a first dielectric layer. A first electrode layer is deposited over the first dielectric layer.

Abstract translation: 描述锗场效应晶体管及其制造方法。 在一个实施例中，该方法包括在衬底上形成氧化锗层并在氧化锗层上形成金属氧化物层。 氧化锗层和金属氧化物层被转换为第一电介质层。 第一电极层沉积在第一介电层上。

公开(公告)号：US20120104578A1

公开(公告)日：2012-05-03

申请号：US13342583

申请日：2012-01-03

Applicant: Hsien-Pin Hu ,  Chen-Hu Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hu Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L23/495

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Abstract translation: 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US20120040500A1

公开(公告)日：2012-02-16

申请号：US12857245

申请日：2010-08-16

Applicant: Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/67126 ,  H01L23/3121 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer.

Abstract translation: 公开了一种用于半导体模制室的系统和方法。 一个实施例包括顶部模制部分和底部模制部分，其在其间放置半导体晶片的它们之间形成空腔。 半导体模制室具有第一组真空管，其保持和固定半导体晶片的位置，以及第二组真空管，其抽空外部环境气体的空腔。 然后可以将密封剂放置在半导体晶片上以便封装半导体晶片。

公开(公告)号：US20120007154A1

公开(公告)日：2012-01-12

申请号：US12834304

申请日：2010-07-12

Applicant: Jing-Cheng Lin ,  Yung-Chi Lin ,  Ku-Feng Yang

Inventor： Jing-Cheng Lin ,  Yung-Chi Lin ,  Ku-Feng Yang

IPC: H01L23/48 ,  H01L29/06 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/11 ,  H01L29/78 ,  H01L2224/131 ,  H01L2924/01029 ,  H01L2924/00014

Abstract: A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Abstract translation: 一种器件包括具有与前表面相对的前表面和后表面的半导体衬底。 绝缘区域从前表面延伸到半导体衬底中。 层间电介质（ILD）在绝缘区域之上。 着陆垫从ILD的顶表面延伸到绝缘区域中。 贯穿基板通孔（TSV）从半导体基板的背面延伸到着陆焊盘。