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公开(公告)号：US09161454B2
公开(公告)日：2015-10-13
申请号：US13726230
申请日：2012-12-24
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen , Shih-Lian Cheng
CPC classification number: H05K3/007 , H01L23/5389 , H01L24/19 , H01L2924/12042 , H05K1/18 , H05K1/183 , H05K1/185 , H05K3/0011 , H05K3/06 , H05K3/30 , H05K3/423 , H05K3/465 , H05K2203/0723 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。
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公开(公告)号：US20140138142A1
公开(公告)日：2014-05-22
申请号：US14164245
申请日：2014-01-26
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Dyi-Chung Hu , Ming-Chih Chen , Tzyy-Jang Tseng
CPC classification number: H01L21/4857 , C25D1/003 , C25D5/022 , C25D5/34 , C25D5/48 , C25D7/12 , H05K1/113 , H05K3/10 , H05K3/424 , H05K3/4647 , H05K3/4682 , H05K2201/10378 , H05K2203/0152 , H05K2203/0733 , Y10T29/49155
Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.
Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。
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公开(公告)号：US20140034361A1
公开(公告)日：2014-02-06
申请号：US14052468
申请日：2013-10-11
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
CPC classification number: H05K1/115 , H05K1/0298 , H05K3/107 , H05K3/421 , H05K2201/0376 , H05K2203/1476 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.
Abstract translation: 提供了包括电路基板，电介质层，第一导电层和第二导电层的电路板。 电路基板具有第一表面和第一电路层。 电介质层设置在电路基板上并覆盖第一表面和第一电路层。 电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔和凹版图案。 第一导电层设置在盲孔内。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层通过第一导电层与第一电路层电连接。
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公开(公告)号：US20240248264A1
公开(公告)日：2024-07-25
申请号：US18623035
申请日：2024-04-01
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Pu-Ju Lin , Kai-Ming Yang , Chen-Hao Lin , Cheng-Ta Ko , Tzyy-Jang Tseng
IPC: G02B6/42 , G02B6/12 , H01L23/498 , H01L25/065
CPC classification number: G02B6/4206 , G02B6/12004 , G02B6/4293 , H01L23/49816 , H01L25/0652
Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.
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公开(公告)号：US20240234371A1
公开(公告)日：2024-07-11
申请号：US18171672
申请日：2023-02-21
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Tzyy-Jang Tseng
IPC: H01L25/065 , H01L23/00 , H01L23/538 , H01L25/00
CPC classification number: H01L25/0655 , H01L23/538 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/80 , H01L24/81 , H01L24/94 , H01L25/50 , H01L2224/05647 , H01L2224/08225 , H01L2224/1132 , H01L2224/1413 , H01L2224/16227 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/81191 , H01L2224/81192 , H01L2224/94 , H01L2924/05442
Abstract: A chip package structure includes a package carrier, a plurality of chips, a bridge and a plurality of solder balls or C4 bumps. The package carrier includes a plurality of carrier pads. The chips are arranged side by side on the package carrier. Each of the chips includes a plurality of first pads and a plurality of second pads. The bridge is located between the chips and the package carrier and includes a plurality of bridge pads. Each of the first pads is hybrid bonded with each of the bridge pads to form a hybrid bonding pad, so that the chips are electrically connected to each other through the bridge. The solder balls are located between the package carrier and the chips. The second pads of each of the chips are electrically connected to the carrier pads of the package carrier through the solder balls.
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Patent Agency Ranking
公开(公告)号：US11923350B2
公开(公告)日：2024-03-05
申请号：US18079884
申请日：2022-12-13
Applicant: Unimicron Technology Corp.
Inventor： Ming-Ru Chen , Tzyy-Jang Tseng , Cheng-Chung Lo
CPC classification number: H01L25/167 , H01L33/62 , H01L33/56 , H01L2933/0066
Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
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公开(公告)号：US20230400649A1
公开(公告)日：2023-12-14
申请号：US17835990
申请日：2022-06-09
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Tzyy-Jang Tseng
IPC: G02B6/42
CPC classification number: G02B6/4274 , G02B6/4295 , H01S5/423 , G02B6/4249 , G02B6/4271
Abstract: A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.
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公开(公告)号：US11690173B2
公开(公告)日：2023-06-27
申请号：US17674837
申请日：2022-02-18
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Chin-Sheng Wang , Ra-Min Tain
CPC classification number: H05K1/0298 , H05K1/023 , H05K1/181 , H05K1/185 , H05K1/032 , H05K1/036 , H05K1/092 , H05K1/113 , H05K2201/0323
Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.
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公开(公告)号：US11665832B2
公开(公告)日：2023-05-30
申请号：US17234805
申请日：2021-04-20
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Chia-Yu Peng , Shao-Chien Lee , Tzyy-Jang Tseng
IPC: H05K1/00 , H05K1/02 , H05K1/03 , H05K1/09 , H05K1/11 , H05K1/14 , H05K1/16 , H05K1/18 , H05K3/20 , H05K3/36 , H05K3/38 , H05K3/40 , H05K3/46 , H05K3/02
CPC classification number: H05K3/46 , H05K3/022 , H05K3/386 , H05K3/4038
Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
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公开(公告)号：US20230067112A1
公开(公告)日：2023-03-02
申请号：US17983396
申请日：2022-11-09
Applicant: Unimicron Technology Corp.
Inventor： Ra-Min Tain , John Hon-Shing Lau , Pu-Ju Lin , Wei-Ci Ye , Chi-Hai Kuo , Cheng-Ta Ko , Tzyy-Jang Tseng
Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.
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