公开(公告)号：US08969257B1

公开(公告)日：2015-03-03

申请号：US12074882

申请日：2008-03-06

Applicant: Zachary Fresco ,  Rich Endo

Inventor： Zachary Fresco ,  Rich Endo

IPC: C40B50/14

CPC classification number: B01J19/0053 ,  B01J2219/00353 ,  B01J2219/00418 ,  B01J2219/00495 ,  H01L21/67023 ,  H01L21/67051 ,  H01L21/6708

Abstract: A reactor assembly having a plurality of reaction chambers defined therein is provided. The reactor assembly includes a fluid flow module that provides a pressurized control flow of fluid from an open container. In another embodiment, the reactor block includes a plurality of passageways defined over a surface of a substrate to accommodate the combinatorial processing in order to obtain multiple data points from a single substrate.

Abstract translation: 提供了一种其中限定有多个反应室的反应器组件。 反应器组件包括流体流动模块，其提供来自开放容器的流体的加压控制流。 在另一个实施例中，反应器块包括限定在衬底的表面上的多个通道，以适应组合处理，以便从单个衬底获得多个数据点。

公开(公告)号：US08962354B2

公开(公告)日：2015-02-24

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66 ,  H01L49/02 ,  C23C14/22 ,  C23C16/455 ,  H01L29/51

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US08961814B2

公开(公告)日：2015-02-24

申请号：US14132383

申请日：2013-12-18

Applicant: Intermolecular Inc.

Inventor： Jeroen Van Duren ,  Zhi-Wen Wen Sun

IPC: C09K13/00 ,  C09K13/04 ,  C09K13/08 ,  C09K13/06 ,  C09K13/02 ,  H01L21/306 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/465 ,  H01L21/70

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods and formulations for the selective etching of etch stop layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. Methods and formulations for the selective etching of molybdenum-based and/or copper-based source/drain electrode layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution.

Abstract translation: 提出了用于选择性蚀刻沉积在制造TFT基显示器件中的金属基半导体层之上的蚀刻停止层的方法和配方。 制剂基于碱性溶液。 提出了用于选择性蚀刻沉积在制造TFT基显示装置中的金属基半导体层之上的钼基和/或铜基源/漏电极层的方法和配方。 制剂基于碱性溶液。

公开(公告)号：US20150035085A1

公开(公告)日：2015-02-05

申请号：US14109728

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.

Abstract translation: 本文提供的实施例描述了高k电介质层和用于形成高k电介质层的方法。 提供基板。 基板包括半导体材料。 将基底暴露于铪前体。 将基底暴露于锆前体。 只有在将基底暴露于铪前体并将基底暴露于锆前体之后，才将基底暴露于氧化剂。 将衬底暴露于铪前体，将衬底暴露于锆前体，以及将衬底暴露于氧化剂引起在衬底上形成一层。 该层包括铪，锆和氧。

公开(公告)号：US08946015B2

公开(公告)日：2015-02-03

申请号：US14333715

申请日：2014-07-17

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Anh Duong ,  Clemens Fitz ,  Olov Karlsson

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/49

CPC classification number: C11D11/0047 ,  C11D7/04 ,  C11D7/08 ,  C11D7/265 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/6704 ,  H01L29/4975 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66568

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract translation: 公开了一种在镍铂硅化过程中从半导体衬底中清除残余物的方法，包括多步残渣清洗，包括将底物暴露于王水溶液中，然后暴露于含有盐酸和过氧化氢的溶液中。 SC2溶液可以与剩余的铂残留物进一步反应，使其更易溶于水溶液，从而从基底表面溶解。

公开(公告)号：US08945952B2

公开(公告)日：2015-02-03

申请号：US14071894

申请日：2013-11-05

Applicant: Intermolecular Inc.

Inventor： John Foster

IPC: H01L21/66 ,  H01L21/302 ,  H01L21/461 ,  C23F1/00 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/8238

CPC classification number: H01L21/30604 ,  H01L21/02071 ,  H01L21/32134 ,  H01L21/67086 ,  H01L21/823828 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract translation: 提供了组合工作流程，用于在形成晶体管器件的栅极结构之后评估清洁过程，为栅极堆叠形成提供优化的工艺条件，包括使用高k电介质的金属栅极堆叠。 NMOS和PMOS晶体管器件组合地制造在衬底的多个区域上，每个区域暴露于不同的清洁化学和工艺。 然后对晶体管器件进行表征，并对数据进行比较，对不同清洁化学品和工艺的潜在损害进行分类。 可以获得优化的化学品和工艺以满足所需的装置要求。

公开(公告)号：US08945414B1

公开(公告)日：2015-02-03

申请号：US14079442

申请日：2013-11-13

Applicant: Intermolecular Inc.

Inventor： Jingang Su ,  Ashish Bodke ,  Abhijit Pethe ,  J Watanabe

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/02046 ,  H01L22/12 ,  H01L22/26

Abstract: Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few Å), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.

Abstract translation: 通过由远程等离子体产生的氟和氧自由基的混合物从下面的硅蚀刻氧化物（例如天然或热氧化硅）。 氧自由基快速氧化任何未覆盖的裸硅区域，防止氟蚀刻裸硅的点蚀比其蚀刻周围氧化物更快。 在该过程之后残留在硅上的非常薄（几埃）的高度均匀的钝化层可能留在原位或去除。 可以立即就地形成不透氧层，以防止进一步的氧化。 单独的氧自由基的预处理在蚀刻开始之前填充氧化物中的孔隙和间隙。

公开(公告)号：US08933429B2

公开(公告)日：2015-01-13

申请号：US13974278

申请日：2013-08-23

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B Phatak

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  H01L21/66

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件开关期间的电压降。 选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括设置在两个较高带隙电介质层之间的低带隙电介质层。 高带隙电介质层可以掺杂掺杂材料以在高于存储器件的工作电压的能级下形成阱。

公开(公告)号：US08925481B2

公开(公告)日：2015-01-06

申请号：US13271449

申请日：2011-10-12

Applicant: ShouQian Shao ,  Jay DeDontney ,  Jason Wright

Inventor： ShouQian Shao ,  Jay DeDontney ,  Jason Wright

IPC: B05C11/10 ,  G01N7/00 ,  C23C16/52 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/45512 ,  C23C16/45557 ,  G01N7/00 ,  Y10T137/0402

Abstract: Systems and methods to determine ozone concentration in a gas mixture of ozone and oxygen, based on measurements of a total mass flow and a corresponding change in a chamber pressure accepting the mixture flow, can enable the measurements of ozone concentration at low pressure settings. The ozone concentration determination can be applied to a vacuum processing chamber, enabling precision semiconductor processing.

Abstract translation: 基于总质量流量的测量和接受混合物流动的室压力的相应变化来确定臭氧和氧气的混合物中的臭氧浓度的系统和方法可以使得能够在低压设置下测量臭氧浓度。 可以将臭氧浓度测定应用于真空处理室，从而实现精密的半导体处理。

公开(公告)号：US08921151B2

公开(公告)日：2014-12-30

申请号：US13737846

申请日：2013-01-09

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Haifan Liang

IPC: H01L31/18 ,  H01L31/0224 ,  H01L31/0236

CPC classification number: H01L31/18 ,  H01L31/022425 ,  H01L31/02366 ,  Y02E10/50

Abstract: Methods for increasing the power output of a TFPV solar panel using thin absorber layers comprise techniques for roughening and/or texturing the back contact layer. The techniques comprise roughening the substrate prior to the back contact deposition, embedding particles in sol-gel films formed on the substrate, and forming multicomponent, polycrystalline films that result in a roughened surface after a wet etch step, etc.

Abstract translation: 使用薄吸收层增加TFPV太阳能电池板的功率输出的方法包括用于粗糙化和/或纹理化背面接触层的技术。 这些技术包括在后接触沉积之前使基底粗糙化，将颗粒嵌入形成在基底上的溶胶 - 凝胶膜中，以及形成在湿蚀刻步骤之后导致粗糙化表面的多组分多晶膜等。