公开(公告)号：US20050176270A1

公开(公告)日：2005-08-11

申请号：US10776359

申请日：2004-02-11

Applicant: Daniel Luch

Inventor： Daniel Luch

IPC: H01R12/00 ,  H01R13/03 ,  H01R43/00 ,  H05K3/24 ,  H05K3/32

CPC classification number: H05K3/242 ,  H01R13/035 ,  H01R43/007 ,  H05K1/0393 ,  H05K3/188 ,  H05K2201/0329 ,  H05K2203/0228 ,  H05K2203/1545 ,  H05K2203/175

Abstract: This invention involves unique electroplated items comprising electrically conductive polymers. In addition, continuous production of electrically treated items is facilitated using electrically conductive resins. Many embodiments employ directly electroplateable resins for particular advantage. Unique methods of establishing electroplated electrical connections are taught.

Abstract translation: 本发明涉及包含导电聚合物的独特电镀物品。 此外，使用导电树脂促进电处理物品的连续生产。 许多实施方案特别适用于直接电镀树脂。 教授建立电镀电连接的独特方法。

公开(公告)号：US06912780B2

公开(公告)日：2005-07-05

申请号：US10860427

申请日：2004-06-03

Applicant: Bruce John Chamberlin ,  Mark Kenneth Hoffmeyer ,  Wai Mon Ma ,  Arch Nuttall ,  James R. Stack

Inventor： Bruce John Chamberlin ,  Mark Kenneth Hoffmeyer ,  Wai Mon Ma ,  Arch Nuttall ,  James R. Stack

IPC: H01R12/00 ,  H05K1/11 ,  H05K3/22 ,  H05K3/40 ,  H05K3/42 ,  H01K3/10

CPC classification number: H05K3/4046 ,  H05K1/112 ,  H05K3/225 ,  H05K3/429 ,  H05K2201/1025 ,  H05K2201/10287 ,  H05K2201/10871 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A method to replace an electrical interface on a printed circuit board having a plurality of contact pads on a top surface, the contact pads being connected to conducting material extending through said circuit board. For the contact pad being replaced, drilling a hole through said printed circuit board at that location, and removing any remaining conductor material attached to the contact pad on the top board surface. Providing a replacement conductor/contact pad structure having a generally T-configuration with a stem and a head that completely surrounds the stem, wherein said head has a diameter greater than the diameter of the drilled hole. Inserting the replacement conductor/contact pad into the hole with said stem extending beyond the second surface of the board with the bottom surface of the head being in contact with the first surface of said board. A replacement conductor/contact pad on repaired board is also described.

Abstract translation: 一种替代在顶表面上具有多个接触焊盘的印刷电路板上的电接口的方法，所述接触焊盘连接到延伸穿过所述电路板的导电材料。 对于更换的接触垫，在该位置穿过所述印刷电路板钻一个孔，并且去除附着在顶板表面上的接触垫上的剩余的导体材料。 提供具有大致T形结构的替换导体/接触垫结构，其具有完全围绕所述杆的杆和头部，其中所述头部的直径大于所述钻孔的直径。 将替换的导体/接触垫插入孔中，其中所述杆延伸超过板的第二表面，并且头的底表面与所述板的第一表面接触。 修理板上的替换导体/接触垫也被描述。

公开(公告)号：US20050133256A1

公开(公告)日：2005-06-23

申请号：US11012496

申请日：2004-12-16

Applicant: Koji Ito

Inventor： Koji Ito

IPC: H05K3/34 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K3/24 ,  H05K3/28 ,  H05K1/11 ,  H01R12/04

CPC classification number: H01L23/4985 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0393 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0397 ,  H05K2203/0191 ,  H05K2203/1545 ,  H05K2203/175 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49204 ,  H01L2924/00

Abstract: A tape substrate includes IC lands electrically connected to pins of a driver IC (integrated circuit), circuit board terminal lands electrically connected to an external circuit board, test lands for testing the driver IC mounted on the tape substrate, and a plating terminal used for plating the land. The test lands are arranged in a matrix. The plating terminal is disposed so as to surround the IC lands, the circuit board terminal lands, and the test lands.

Abstract translation: 带状基板包括电连接到驱动器IC（集成电路）的引脚的IC焊盘，电连接到外部电路板的电路板端子焊盘，用于测试安装在带基板上的驱动器IC的测试焊盘，以及用于 电镀土地。 试验台排列成矩阵。 电镀端子被设置成围绕IC焊盘，电路板端子焊盘和测试焊盘。

公开(公告)号：US20050114816A1

公开(公告)日：2005-05-26

申请号：US11018440

申请日：2004-12-21

Applicant: Albert Yeh ,  Regina Pabilonia ,  Robert Kressin ,  Wei Liu

Inventor： Albert Yeh ,  Regina Pabilonia ,  Robert Kressin ,  Wei Liu

IPC: B23K26/00 ,  H01L21/66 ,  H01L23/525 ,  H05K3/22 ,  G06F17/50 ,  G06F19/00

CPC classification number: H01L22/22 ,  B23K26/351 ,  H01L21/485 ,  H01L23/525 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/056 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/16 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09918 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49131 ,  Y10T29/49156 ,  Y10T29/4973 ,  Y10T29/49789 ,  Y10T29/49798 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a parallel design process for ICs, plural circuit features to be evaluated are laid out while designing an IC. Plural ICs are then fabricated and packaged. For a first packaged IC, an interior circuit feature coupled to at least one of the plural circuit features to be evaluated is identified. A trimming point on the interior circuit feature is identified using an x-ray inspection system; coordinates of the trimming point are related to coordinates of a visible reference marker; and the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. The cutting tool is used to cut into the first packaged IC until the interior circuit feature has been acceptably modified at the trimming point. Operation of the first packaged IC is compared to operation of a second packaged IC. Other parallel design processes are also disclosed.

Abstract translation: 在IC的并行设计过程中，在设计IC时布置要评估的多个电路特征。 然后制造和包装多个IC。 对于第一封装IC，识别耦合到待评估的多个电路特征中的至少一个的内部电路特征。 使用X射线检查系统识别室内电路特征上的修整点; 修剪点的坐标与可见参考标记的坐标相关; 并且使用可见参考标记和修剪点之间的关系来将切割工具定位在修剪点上。 切割工具用于切入第一封装IC，直到内部电路特征在修剪点被可接受地修改为止。 将第一封装IC的操作与第二封装IC的操作进行比较。 还公开了其他并行设计过程。

公开(公告)号：US06872896B1

公开(公告)日：2005-03-29

申请号：US10241745

申请日：2002-09-11

Applicant: Steven R. Young ,  Fredrick V. Hayen ,  Joshua J. Harmala

Inventor： Steven R. Young ,  Fredrick V. Hayen ,  Joshua J. Harmala

IPC: G11B5/48 ,  H01H1/12 ,  H01H15/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/05

CPC classification number: G11B5/455 ,  G11B5/40 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0259 ,  H05K1/0293 ,  H05K1/0393 ,  H05K1/056 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2203/175

Abstract: Structure for forming a switchable shunt for a suspension assembly having conductive, insulating and metal base layers. The shunt includes a bridge in the conductive layer with either a continuous connection or small gap between ends of the bridge. The continuous connection of the bridge is severed either by temporarily moving the lands out of their original plane by stretching and rupturing the bridge or by shearing the continuous connection of the bridge. For the sheared or gapped bridge, at least one end of the bridge is moved out of the plane, compressed and elongated. When released, the separated ends of the bridge overlap and contact each other to form a normally-closed switch. To subsequently open the switchable shunt, at least one of the lands is moved out of plane to physically and electrically open the connection between the separated and overlapped ends of the bridge.

Abstract translation: 用于形成具有导电，绝缘和金属基底层的悬挂组件的可切换分流器的结构。 分流器包括在导电层中的桥，其中桥与连接端之间具有连续连接或小间隙。 桥的连续连接通过暂时地将平台从其原始平面移动，通过拉伸和破裂桥梁或者通过剪切桥的连续连接来切断。 对于剪切或有间隙的桥梁，桥梁的至少一端移出平面，压缩并伸长。 当释放时，桥的分离端重叠并彼此接触以形成常闭开关。 为了随后打开可切换分路，至少一个平台被移出平面以物理上和电气地打开桥的分离和重叠的端部之间的连接。

公开(公告)号：US20050063135A1

公开(公告)日：2005-03-24

申请号：US10664638

申请日：2003-09-18

Applicant: William Borland ,  Xin Fang

Inventor： William Borland ,  Xin Fang

IPC: H01G4/01 ,  H01G4/255 ,  H05K1/09 ,  H05K1/16 ,  H05K3/22 ,  H05K3/42 ,  H05K3/46 ,  H01G4/005

CPC classification number: H01G4/01 ,  H01G4/255 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: In a printed wiring board, capacitors have electrode layers that may be selectively trimmed to obtain high tolerances. The electrode layers can be formed from a plurality of elongated electrode portions, each of which can be selectively trimmed. The electrode layers can also be formed from interdigitated elongated electrode portions.

公开(公告)号：US20040245242A1

公开(公告)日：2004-12-09

申请号：US10456223

申请日：2003-06-06

Inventor： Daniel J. Byrne ,  Amol S. Pandit ,  Mark N. Robins

IPC: H05B001/02

CPC classification number: H05K1/0212 ,  H05K1/0259 ,  H05K1/0293 ,  H05K2201/0305 ,  H05K2201/10181 ,  H05K2203/105 ,  H05K2203/173 ,  H05K2203/175

Abstract: The present invention in situ reconfigures connections within an electric circuit, such that a previously open circuit becomes a permanent in situ electrical pathway. A heat-activated electrical coupling comprises a heat-activated coupler and a heater. The heat-activated coupler comprises a preform of a material that changes a physical or electrical state in response to heat from the heater to bridge a gap between separate but adjacent ends of respective circuit traces. An in situ reconfigurable circuit comprises the heat-activated electrical coupling, a fusible link, a primary circuit and a secondary or back-up circuit. An in situ recoverable electrostatic discharge (ESD) circuit comprises the heat-activated electrical coupling, a primary ESD protection portion, and a secondary or back-up ESD protection portion. A method of in situ reconfiguring a circuit comprises creating the heat-activated electrical coupling and activating the electrical coupling with heat.

Abstract translation: 本发明原位重新配置电路内的连接，使得先前的开路成为永久的原位电路径。 热激活电耦合包括热激活耦合器和加热器。 热激活耦合器包括材料的预成型件，其响应于来自加热器的热而改变物理或电气状态，以桥接各个电路迹线的分开但相邻端之间的间隙。 原位可重构电路包括热启动电耦合，可熔链路，初级电路和次级或备用电路。 原位可恢复静电放电（ESD）电路包括热激活电耦合，初级ESD保护部分和次级或备用ESD保护部分。 一种原位重构电路的方法包括产生热激活电耦合并且用热激活电耦合。

公开(公告)号：US20040226828A1

公开(公告)日：2004-11-18

申请号：US10813778

申请日：2004-03-31

Inventor： Kiyoshi Mita

IPC: C25D005/02

CPC classification number: H05K3/242 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/0052 ,  H05K2203/1572 ,  H05K2203/175 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided are a method for manufacturing a mounting substrate and a method for manufacturing a circuit device, both of which include the step of electroplating a number of electrodes. The method for manufacturing a mounting substrateincludes the steps of: forming a plurality of electrodes to a mounting substrate, the plurality of electrodes being electrically connected to each other by use of plating wires; energizing the electrodes via the plating wires to coat the electrodes with plated films 19 by electroplating; and electrically separating the individual electrodes from each other by cutting off the plating wires. Furthermore, the method for manufacturing a circuit device includes, in addition to the foregoing method for manufacturing a mounting substrate, the steps of: fixing a circuit element on the mounting substrate and electrically connecting the electrodes with the circuit element; and forming a sealing resin so as to cover the circuit element.

Abstract translation: 提供一种用于制造安装基板的方法和用于制造电路器件的方法，二者包括电镀多个电极的步骤。 制造安装基板的方法包括以下步骤：将多个电极形成到安装基板，多个电极通过电镀线彼此电连接; 通过电镀线对电极通电，通过电镀将电极涂覆在电镀膜19上; 并且通过切断电镀线将各个电极彼此电分离。 此外，制造电路装置的方法除了上述制造安装基板的方法之外还包括以下步骤：将电路元件固定在安装基板上并将电极与电路元件电连接; 并形成密封树脂以覆盖电路元件。

公开(公告)号：US20040150961A1

公开(公告)日：2004-08-05

申请号：US10355807

申请日：2003-01-30

Inventor： Jeffrey Michael Frechette

IPC: H05K001/14

CPC classification number: H05K1/0293 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/09127 ,  H05K2203/175

Abstract: A multi-state indicator includes a section connecting a first trace to a second trace adapted to facilitate application of force to said section to disconnect said section from said first and/or second trace(s) and to disconnect said first trace from said second trace. In addition, the multi-state indicator includes circuitry to indicate a state based on whether said first trace connects to said second trace.

Abstract translation: 多状态指示器包括将第一迹线连接到第二迹线的部分，其适于便于向所述部分施加力以将所述部分与所述第一和/或第二迹线断开，并将所述第一迹线与所述第二迹线断开 。 另外，多状态指示器包括基于所述第一迹线是否连接到所述第二迹线来指示状态的电路。

公开(公告)号：US20040118605A1

公开(公告)日：2004-06-24

申请号：US10328292

申请日：2002-12-20

Inventor： Ruud van der Laan

IPC: H05K001/11 ,  H05K003/42

CPC classification number: H05K3/429 ,  H05K3/0008 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/0242 ,  H05K2203/167 ,  H05K2203/175 ,  Y10T29/49165

Abstract: A printed circuit board, comprising a substrate, a first conductor and a second conductor. The substrate having an interior surface defining a hole. The first conductor is disposed within the hole. The second conductor is disposed within the hole. The first conductor is insulated from the second conductor.

Abstract translation: 一种印刷电路板，包括基板，第一导体和第二导体。 衬底具有限定孔的内表面。 第一导体设置在孔内。 第二导体设置在孔内。 第一导体与第二导体绝缘。