公开(公告)号：US08920618B2

公开(公告)日：2014-12-30

申请号：US13339648

申请日：2011-12-29

Applicant: Hong Sheng Yang ,  Zhendong Hong ,  Chi-I Lang

Inventor： Hong Sheng Yang ,  Zhendong Hong ,  Chi-I Lang

IPC: C23C14/54

CPC classification number: C23C14/044 ,  C23C14/3464

Abstract: Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.

Abstract translation: 公开了用于将沉积层沉积到基底上的高沉积速率溅射的装置和方法。 设备通常包括处理室; 设置在处理室内的一个或多个溅射源，其中每个溅射源包括溅射靶; 设置在所述处理室内的衬底支撑件; 位于所述溅射源和所述衬底之间的屏蔽罩，所述屏蔽件包括位于每个溅射源下方的孔; 以及连接到所述基板支撑件的输送系统，其能够定位所述基板，使得所述基板上的多个位置隔离区域中的一个可以通过位于每个所述溅射源下方的所述孔暴露于溅射材料; 其中溅射靶和衬底之间的间距小于100mm。 该装置能够在衬底上的位置分离区域上实现高沉积速率溅射。

公开(公告)号：US08913418B2

公开(公告)日：2014-12-16

申请号：US13891472

申请日：2013-05-10

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Vidyut Gopal ,  Chien-Lan Hsueh

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

公开(公告)号：US08907314B2

公开(公告)日：2014-12-09

申请号：US13727958

申请日：2012-12-27

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

公开(公告)号：US08906160B2

公开(公告)日：2014-12-09

申请号：US12978403

申请日：2010-12-23

Applicant: Richard Endo ,  Edward Haywood

Inventor： Richard Endo ,  Edward Haywood

IPC: C23C16/455 ,  C23C16/40 ,  C23C16/44

CPC classification number: C23C16/45587 ,  C23C16/4401 ,  C23C16/4408 ,  C23C16/4412 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/45565 ,  C23C16/45574

Abstract: Embodiments of the present invention provide vapor deposition tools. In one example, a vapor deposition tool includes housing. A substrate support is positioned within the housing and configured to support a substrate. A backing plate is positioned above the substrate support. A showerhead is positioned between the substrate support and the backing plate and has a plurality of openings therethrough. A fluid trap member is positioned around a periphery of the showerhead. A fluid trap member actuator is coupled to the fluid trap member and configured to move the fluid trap member between first and second positions relative to the backing plate.

Abstract translation: 本发明的实施例提供蒸镀工具。 在一个实例中，气相沉积工具包括壳体。 衬底支撑件定位在壳体内并且构造成支撑衬底。 衬板位于衬底支架上方。 喷头位于基板支撑件和背板之间，并且具有穿过其中的多个开口。 流体捕获构件围绕喷头的周边定位。 流体捕集器构件致动器联接到流体捕获构件并且构造成使流体捕获构件相对于背板在第一和第二位置之间移动。

公开(公告)号：US08900422B2

公开(公告)日：2014-12-02

申请号：US12921776

申请日：2009-04-17

Applicant: Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

Inventor： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: B05D5/12 ,  C23C14/34 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08895951B2

公开(公告)日：2014-11-25

申请号：US13249631

申请日：2011-09-30

Applicant: Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

Inventor： Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

IPC: H01L47/00 ,  C23C14/08 ,  C23C14/00 ,  C23C14/54 ,  H01L45/00 ,  H01L27/24

CPC classification number: C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 根据该方法制造的这种电池的多电平存储器单元或阵列可以针对一组给定材料制造为具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或最大“on” 电流“off”电流（Ion / Ioff）。

公开(公告)号：US08889492B2

公开(公告)日：2014-11-18

申请号：US14259411

申请日：2014-04-23

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Tony P. Chiang

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

公开(公告)号：US08882914B2

公开(公告)日：2014-11-11

申请号：US11418689

申请日：2006-05-05

Applicant: Tony P. Chiang ,  David E. Lazovsky ,  Sandra G. Malhotra

Inventor： Tony P. Chiang ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: C23C16/00 ,  C23C14/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/677 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01L21/32051 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76871

Abstract: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Abstract translation: 描述了用于处理具有两个或更多个区域的基板的基板处理系统和方法。 该处理包括分子自组装和组合处理中的一种或多种。 材料，工艺，加工条件，材料应用顺序和工艺顺序中的至少一个不同于衬底相对于衬底的至少一个其它区域的至少一个区域中的处理。 描述了包括许多处理模块的处理系统。 模块包括配置用于衬底的分子自组装和组合处理中的一个或多个的位点隔离反应器（SIR）。

公开(公告)号：US08878269B2

公开(公告)日：2014-11-04

申请号：US13738831

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

IPC: H01L27/108

CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

公开(公告)号：US08878151B2

公开(公告)日：2014-11-04

申请号：US13331650

申请日：2011-12-20

Applicant: Tony Chiang

Inventor： Tony Chiang

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract translation: 提供多个非易失性存储器元件。 多个非易失性存储器元件包含多个层。 每个层可以基于不同的双稳态材料。 双稳态材料可以是电阻式开关材料，例如电阻式开关金属氧化物。 可选导体层和电流导向元件可以与双稳电阻开关金属氧化物层串联连接。