公开(公告)号：US20180219079A1

公开(公告)日：2018-08-02

申请号：US15938412

申请日：2018-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

公开(公告)号：US10014297B1

公开(公告)日：2018-07-03

申请号：US15589312

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Wenhui Wang ,  Xunyuan Zhang ,  Ruilong Xie ,  Jia Zeng ,  Xuelian Zhu ,  Min Gyu Sung ,  Shao Beng Law

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/6681

Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.

公开(公告)号：US20180182867A1

公开(公告)日：2018-06-28

申请号：US15901447

申请日：2018-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US10008577B2

公开(公告)日：2018-06-26

申请号：US15225152

申请日：2016-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L27/00 ,  H01L21/00 ,  H01L29/49 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

公开(公告)号：US20180174855A1

公开(公告)日：2018-06-21

申请号：US15890859

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US10002932B2

公开(公告)日：2018-06-19

申请号：US15345137

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim ,  Chanro Park

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/665

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20180166335A1

公开(公告)日：2018-06-14

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US20180130895A1

公开(公告)日：2018-05-10

申请号：US15345644

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09966430B2

公开(公告)日：2018-05-08

申请号：US15202983

申请日：2016-07-06

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US20180102432A1

公开(公告)日：2018-04-12

申请号：US15693938

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7827 ,  H01L21/02614 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/41741 ,  H01L29/66553 ,  H01L29/66666

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.