公开(公告)号：US09576827B2

公开(公告)日：2017-02-21

申请号：US14298692

申请日：2014-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Yen-Chang Chu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Ru-Liang Lee

IPC分类号： H01L23/00 ,  H01L21/67 ,  H01L25/00 ,  B23B31/30

CPC分类号： H01L21/67092 ,  B23B31/305 ,  B23B31/307 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/3511 ,  Y10T156/14 ,  H01L2224/80 ,  H01L2224/80001

摘要： A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

摘要翻译： 提供了将第一晶片接合到第二晶片的系统和方法。 第二晶片卡盘具有第二表面，第二表面的轮廓可由轮廓控制层调节。 将第一晶片放置在第一晶片卡盘的第一表面上，并且将第二晶片放置在第二晶片卡盘的第二表面上。 第一晶片和第二晶片在接合之前变形，分别形成第一翘曲晶片和第二翘曲晶片。 第一个翘曲的晶片与第二个翘曲晶片接合。

公开(公告)号：US09527188B2

公开(公告)日：2016-12-27

申请号：US13629889

申请日：2012-09-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： B24B9/06 ,  B24D7/18 ,  B24B1/04

CPC分类号： B24D7/18 ,  B24B1/04 ,  B24B9/065

摘要： A grinding wheel for wafer edge trimming includes a head having an open side and an abrasive end bonded around an edge of the open side of the head. The abrasive end is arranged to have multiple simultaneous contacts around a wafer edge during the wafer edge trimming.

摘要翻译： 用于晶片边缘修剪的砂轮包括具有开口侧的头部和结合在头部的敞开侧的边缘周围的研磨端。 研磨端设置成在晶片边缘修整期间具有围绕晶片边缘的多个同时接触。

公开(公告)号：US20160358882A1

公开(公告)日：2016-12-08

申请号：US15238532

申请日：2016-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Lan-Lin Chao ,  Cheng-Tai Hsiao ,  Xin-Hua Huang ,  Hsun-Chung Kuang

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/80 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/0657 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/0516 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/8084 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/8192 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001

摘要： A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.

公开(公告)号：US09257399B2

公开(公告)日：2016-02-09

申请号：US14056345

申请日：2013-10-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L25/065 ,  H01L25/04 ,  H01L25/075 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L21/76883 ,  H01L21/76805 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/10 ,  H01L24/18 ,  H01L24/80 ,  H01L24/89 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2225/06513 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

摘要翻译： 集成电路结构包括封装部件，该封装部件还包括具有第一孔隙率的无孔介电层，以及在无孔介电层上方和与无孔介电层接触的多孔电介质层，其中多孔介电层具有高于 第一孔隙度。 接合垫穿透无孔介电层和多孔介电层。 电介质阻挡层覆盖并与多孔电介质层接触。 接合焊盘通过介电阻挡层露出。 电介质阻挡层具有平坦的顶表面。 接合焊盘具有比介电阻挡层的底表面高的平面顶表面。

公开(公告)号：US20150357226A1

公开(公告)日：2015-12-10

申请号：US14298692

申请日：2014-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Yen-Chang Chu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Ru-Liang Lee

IPC分类号： H01L21/683 ,  H01L21/67 ,  B23B31/30 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L21/67092 ,  B23B31/305 ,  B23B31/307 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/3511 ,  Y10T156/14 ,  H01L2224/80 ,  H01L2224/80001

摘要： A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

摘要翻译： 提供了将第一晶片接合到第二晶片的系统和方法。 第二晶片卡盘具有第二表面，第二表面的轮廓可由轮廓控制层调节。 将第一晶片放置在第一晶片卡盘的第一表面上，并且将第二晶片放置在第二晶片卡盘的第二表面上。 第一晶片和第二晶片在接合之前变形，分别形成第一翘曲晶片和第二翘曲晶片。 第一个翘曲的晶片与第二个翘曲晶片接合。

公开(公告)号：US20150108644A1

公开(公告)日：2015-04-23

申请号：US14056345

申请日：2013-10-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L21/76883 ,  H01L21/76805 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/10 ,  H01L24/18 ,  H01L24/80 ,  H01L24/89 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2225/06513 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

摘要翻译： 集成电路结构包括封装部件，该封装部件还包括具有第一孔隙率的无孔介电层，以及在无孔介电层上方和与无孔介电层接触的多孔电介质层，其中多孔介电层具有高于 第一孔隙度。 接合垫穿透无孔介电层和多孔介电层。 电介质阻挡层覆盖并与多孔电介质层接触。 接合焊盘通过介电阻挡层露出。 电介质阻挡层具有平坦的顶表面。 接合焊盘具有比介电阻挡层的底表面高的平面顶表面。

公开(公告)号：US20140263586A1

公开(公告)日：2014-09-18

申请号：US13888921

申请日：2013-05-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Xin-Chung Kuang ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： B23K1/20

CPC分类号： H01L21/02068 ,  B23K1/0016 ,  B23K1/206 ,  B23K20/026 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/40 ,  B23K2101/42 ,  H01L24/89 ,  H01L2224/80894

摘要： A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

摘要翻译： 一种方法包括在第一包装部件的表面上执行等离子体激活，从第一包装部件的金属焊盘的表面去除氧化物区域，以及执行预接合以将第一包装部件结合到第二包装部件。

公开(公告)号：US20140256087A1

公开(公告)日：2014-09-11

申请号：US13787566

申请日：2013-03-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ping-Yin Liu ,  Xin-Hua Huang ,  Chih-Hui Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Yan-Chih Lu ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/757 ,  H01L2224/7598 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80121 ,  H01L2224/80204 ,  H01L2224/80209 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/00

摘要： A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded pair, first metal pads in the first package component are bonded to second metal pads in the second package component, and a first surface dielectric layer at a surface of the first package component is bonded to a second surface dielectric layer at a surface of the second package component. After the hybrid bonding, a thermal compressive annealing is performed on the bonded pair.

摘要翻译： 一种方法包括执行混合结合以将第一封装部件结合到第二封装部件，从而形成结合对。 在结合对中，第一封装部件中的第一金属焊盘接合到第二封装部件中的第二金属焊盘，并且在第一封装部件的表面处的第一表面电介质层在表面 的第二个包装组件。 在混合键合之后，对结合对进行热压缩退火。

公开(公告)号：US20140154841A1

公开(公告)日：2014-06-05

申请号：US14174214

申请日：2014-02-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Richard Chu ,  Martin Liu ,  Chia-Hua Chu ,  Yuan-Chih Hsieh ,  Chung-Hsien Lin ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Mingo Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/94 ,  B81B2207/015 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/0771 ,  H01L23/481 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

摘要翻译： 提供晶圆级封装。 该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。 所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。 其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。

公开(公告)号：US20140113398A1

公开(公告)日：2014-04-24

申请号：US14136996

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Jui Wang ,  Szu-Ying Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC分类号： H01L27/146

CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

摘要翻译： 背面照明图像传感器包括光电二极管和位于第一芯片中的第一晶体管，其中第一晶体管电耦合到光电二极管。 背面照明图像传感器还包括形成在第二芯片中的第二晶体管和形成在第三芯片中的多个逻辑电路，其中第二芯片堆叠在第一芯片上，第三芯片堆叠在第二芯片上。 逻辑电路，第二晶体管和第一晶体管通过多个焊盘和通孔彼此耦合。