Abstract:
A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.
Abstract:
A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.
Abstract:
A solar collector includes a substrate having a top surface and a bottom surface opposite to the upper surface, a sidewall, a transparent cover, and a heat-absorbing layer. The sidewall is arranged on the top surface of the substrate. The transparent cover is disposed on the sidewall opposite to the substrate to form a sealed chamber with the substrate together. The heat-absorbing layer is disposed on the upper surface of the substrate and includes a carbon nanotube film having a plurality of carbon nanotubes. The carbon nanotubes in the carbon nanotube film are entangled with each other.
Abstract:
An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base.
Abstract:
Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.
Abstract:
A wireless charger includes a charging platform and a capacitive touch device. The capacitive touch device includes a first touch-sensitive layer, a second touch-sensitive layer, and a microcontroller. The capacitive touch device is disposed over the charging platform for sensing a position of the electronic device.
Abstract:
A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die.
Abstract:
An electronic device includes a housing, a capacitive touch button, a PCB and a connection mechanism. The capacitive touch button is secured in the housing and includes a number of button bodies. The PCB is secured in the housing. The connection mechanism includes a circuit board and a connection element. The circuit board is secured in the housing and includes a number of sensor electrodes and a number of electrical protrusions, which are all arranged corresponding to the number of button bodies of the capacitive touch button. The sensor electrodes are connected to the capacitive touch button and the electrical protrusions. The connection element includes a first end and a second end. The first end is fixed on the PCB. The second end resists against the electrical protrusions for electrically connecting the capacitive touch button and the controller of the PCB.
Abstract:
A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.
Abstract:
Described is a polyurethane wire enamel composed of at least one blocked polyisocyanate adduct, blocked with alkylphenols, at least one hydroxy polyester comprising ester and/or imide and/or amide groups, at least one hydrocarbon-based organic solvent, and further auxiliaries and additives.