公开(公告)号：US09673158B2

公开(公告)日：2017-06-06

申请号：US14630265

申请日：2015-02-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Chien-Hsun Lee

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/16 ,  H01L24/18 ,  H01L24/81 ,  H01L2224/02379 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11515 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2224/64

摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

公开(公告)号：US08987605B2

公开(公告)日：2015-03-24

申请号：US13247529

申请日：2011-09-28

申请人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Chien-Hsiun Lee

发明人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Chien-Hsiun Lee

IPC分类号： H05K1/09 ,  B23K31/02 ,  B23K1/20 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/16 ,  H01L24/18 ,  H01L24/81 ,  H01L2224/02379 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11515 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2224/64

摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

摘要翻译： 一种器件包括衬底，衬底上的金属焊盘以及具有在金属焊盘上的部分的钝化层。 后钝化互连（PPI）电耦合到金属焊盘，其中PPI包括在金属焊盘和钝化层上的部分。 聚合物层在PPI之上。 焊球在PPI之上。 化合物包括邻接焊球和聚合物层的部分，其中所述化合物包括助熔剂和聚合物。

公开(公告)号：US20080197505A1

公开(公告)日：2008-08-21

申请号：US12032730

申请日：2008-02-18

申请人： Tatsuhiko ASAKAWA

发明人： Tatsuhiko ASAKAWA

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/11515 ,  H01L2224/1191 ,  H01L2224/13008 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1369 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/0665 ,  H01L2924/00014

摘要： A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film.

摘要翻译： 半导体器件包括：具有集成电路的半导体衬底，形成在集成电路上方的钝化膜，以及与该集成电路电连接的电极，该钝化膜具有不平坦表面，该电极具有至少部分暴露于 钝化膜; 设置在所述钝化膜上的第一树脂层; 覆盖所述钝化膜和所述第一树脂层的第二树脂层; 以及从电极延伸到第一树脂层上方的第二树脂层的第一部分的布线，电极通过钝化膜上方的第二树脂层的第二部分。

公开(公告)号：US20180320029A1

公开(公告)日：2018-11-08

申请号：US15769189

申请日：2016-11-02

申请人： LINTEC Corporation

发明人： Masanori YAMAGISHI ,  Akinori SATO

IPC分类号： C09J7/25 ,  C09J7/38 ,  C08L63/00 ,  H01L23/00

CPC分类号： C09J7/25 ,  C08L63/00 ,  C08L2203/16 ,  C08L2203/20 ,  C09J7/00 ,  C09J7/20 ,  C09J7/38 ,  C09J163/00 ,  H01L24/26 ,  H01L2224/11 ,  H01L2224/11515

摘要： A curable resin film of the present invention forms a first protective film (1a) by attaching the curable resin film containing an epoxy-based thermosetting component having a weight-average molecular weight of 200 to 4,000 to a surface (5a) of a semiconductor wafer (5) having a plurality of bumps (51) with an average peak height (h1) of 50 to 400 μm, an average diameter of 60 to 500 μm, and an average pitch of 100 to 800 μm, heating the attached curable resin film at 100° C. to 200° C. for 0.5 to 3 hours, and curing the heated curable resin film, and when longitudinal sections thereof are observed by a scanning electron microscope, a ratio (h3/h1) of an average thickness (h3) of the first protective film (1a) at a center position between the bumps (51) to an average peak height (h1) of the bumps (51), and a ratio (h2/h1) of an average thickness (h2) of the first protective film (1a) at a position being in contact with the plurality of bumps (51) to the average peak height (h1) satisfy a relationship represented by the following expression of [{(h2/h1)−(h3/h1)}≤0.1].

公开(公告)号：US08067305B2

公开(公告)日：2011-11-29

申请号：US12231457

申请日：2008-09-03

申请人： Arthur W. Zafiropoulo ,  Andrew M. Hawryluk

发明人： Arthur W. Zafiropoulo ,  Andrew M. Hawryluk

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  B33Y80/00 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11442 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11515 ,  H01L2224/1155 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.

摘要翻译： 提供了在基板（例如半导体晶片）的基本平坦的表面上形成所需三维形状的导电结构的方法。 通常，颗粒物质以层叠的方式沉积并粘附到基底表面上的选定区域。 可以沉积颗粒物质以产生用于形成结构的模具和/或产生结构本身。 可以使用具有相关联的电子数据的三维打印机，而不需要光刻掩模或掩模版。

公开(公告)号：US07834453B2

公开(公告)日：2010-11-16

申请号：US11762729

申请日：2007-06-13

申请人： Shyh-Ming Chang

发明人： Shyh-Ming Chang

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/4007 ,  H01L22/32 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/11515 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/13552 ,  H01L2224/13553 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/2919 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09909 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A contact structure including a contact pad, a polymer bump and a conductive layer is provided in the present invention. The contact pad is disposed on a substrate. The polymer bump is disposed on the contact pad. The conductive layer covers the polymer bump and extends to the outside of the polymer bump. The portion of the conductive layer extending to the outside of the polymer bump serves as a test pad. The invention further discloses a manufacturing method of a contact structure. First, a substrate is provided having a contact pad already formed thereon. Then, a polymer bump is formed on the contact pad and a conductive layer is formed on the polymer bump. The conductive layer covers the polymer bump and extends to the outside of the polymer bump. The portion of the conductive layer extending to the outside of the polymer bump serves as a test pad.

摘要翻译： 在本发明中提供了包括接触垫，聚合物凸块和导电层的接触结构。 接触垫设置在基板上。 聚合物凸块设置在接触垫上。 导电层覆盖聚合物凸块并延伸到聚合物凸块的外部。 延伸到聚合物凸块外部的导电层的部分用作测试垫。 本发明还公开了一种接触结构的制造方法。 首先，提供具有已在其上形成的接触垫的基板。 然后，在接触焊盘上形成聚合物凸块，并且在聚合物凸块上形成导电层。 导电层覆盖聚合物凸块并延伸到聚合物凸块的外部。 延伸到聚合物凸块外部的导电层的部分用作测试垫。

公开(公告)号：US07750468B2

公开(公告)日：2010-07-06

申请号：US12032730

申请日：2008-02-18

申请人： Tatsuhiko Asakawa

发明人： Tatsuhiko Asakawa

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/11515 ,  H01L2224/1191 ,  H01L2224/13008 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1369 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/0665 ,  H01L2924/00014

摘要： A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film.

摘要翻译： 半导体器件包括：具有集成电路的半导体衬底，形成在集成电路上方的钝化膜，以及与该集成电路电连接的电极，该钝化膜具有不平坦表面，该电极具有至少部分暴露于 钝化膜; 设置在所述钝化膜上的第一树脂层; 覆盖所述钝化膜和所述第一树脂层的第二树脂层; 以及从电极延伸到第一树脂层上方的第二树脂层的第一部分的布线，电极通过钝化膜上方的第二树脂层的第二部分。

公开(公告)号：US06940175B2

公开(公告)日：2005-09-06

申请号：US10163497

申请日：2002-06-07

申请人： Yoshihide Iwazaki ,  Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori

发明人： Yoshihide Iwazaki ,  Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori

IPC分类号： H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/12 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11515 ,  H01L2224/11901 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/138 ,  H01L2224/16145 ,  H01L2224/81192 ,  H01L2224/81855 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/1216 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/1476 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13099 ,  H01L2224/05599

摘要： A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin. A manufacturing method of the semiconductor device includes the steps of: forming the spacers on first electrode pads by hardening the liquid resin material; providing the liquid conductive combining material on either the first electrode pads or second electrode pads; aligning the first electronic component with the second electronic component so that (i) the spacers contact with the second electrode pads and (ii) the liquid conductive combining material contact with either at least a part of one the first electrode pads or at least part of one of the second electrode pads; and combining the first electronic component with the second electronic component by hardening the liquid conductive combining material. The steps above are carried out in this order.

摘要翻译： 半导体器件包括（i）第一电子部件和第二电子部件之间的间隔物，用于保持第一和第二电子部件之间的距离恒定，以及（ii）组合用于将第一电子部件与第二电子部件组合的部件 零件。 间隔件由由热固性树脂制成的液体树脂材料制成，并且组合部分由包括金属和热固性树脂的液体导电组合材料制成。 半导体器件的制造方法包括以下步骤：通过使液体树脂材料硬化来在第一电极焊盘上形成间隔物; 在第一电极焊盘或第二电极焊盘上提供液体导电组合材料; 将第一电子部件与第二电子部件对准，使得（i）间隔件与第二电极焊盘接触，和（ii）液体导电组合材料与第一电​​极焊盘的至少一部分或至少部分 第二电极焊盘之一; 以及通过硬化所述液体导电组合材料来将所述第一电子部件与所述第二电子部件组合。 上述步骤按此顺序进行。

公开(公告)号：US09532495B2

公开(公告)日：2016-12-27

申请号：US14062767

申请日：2013-10-24

申请人： MURATA MANUFACTURING CO., LTD.

发明人： Shinya Kiyono ,  Yoshiaki Satake

IPC分类号： H05K3/34 ,  H05K13/04 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/11312 ,  H01L2224/11318 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11505 ,  H01L2224/11515 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/16052 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17104 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/3025 ,  H01L2924/3841 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3457 ,  H05K13/0465 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

摘要翻译： 制造电子部件模块的方法和通过该制造方法制造的电子部件模块包括凸块，每个凸起包括具有较大厚度的较厚部分和较薄部分，并且形成在基板的一个表面上。 当以俯视图看待安装状态的电子部件时，较厚部分位于靠近电子部件中心的相应外端子的一侧，较薄部分位于相应外部的相对侧 终奌站。 在平面图中，分别将外端子连接到凸块的接合部分形成为使得相对侧上的每个接合部分的高度低于靠近电子部件中心的一侧的接合部分的高度。

公开(公告)号：US20160233184A1

公开(公告)日：2016-08-11

申请号：US15024552

申请日：2014-09-19

申请人： NITTO DENKO CORPORATION

发明人： Hiroyuki Hanazono ,  Naohide Takamoto ,  Akihiro Fukui

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L21/48 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/11019 ,  H01L2224/11502 ,  H01L2224/11515 ,  H01L2224/1155 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29371 ,  H01L2224/29387 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83

摘要： A method for manufacturing a semiconductor includes: a Step A of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a semiconductor chip, a Step B of preparing an adherend, a Step C of pasting the chip with sheet-shaped resin composition onto the adherend so that the sheet-shaped resin composition serves as a pasting surface, a Step D of heating the sheet-shaped resin composition to semi-cure the sheet-shaped resin composition after the Step C, and a Step E of heating the sheet-shaped resin composition at a higher temperature than in the Step D to cure the sheet-shaped resin composition after the Step D.

摘要翻译： 半导体的制造方法包括：将片状树脂组合物贴合在半导体芯片上的片状树脂组合物的制备工序A，制造被粘物的工序B，粘贴 将片状树脂组合物与片状树脂组合物贴合在被粘物上，使得片状树脂组合物作为糊状表面，在步骤C之后加热片状树脂组合物以使片状树脂组合物半固化的步骤D， 以及步骤E，其在比步骤D更高的温度下加热片状树脂组合物，以在步骤D之后固化片状树脂组合物。