公开(公告)号：US08945991B2

公开(公告)日：2015-02-03

申请号：US14087445

申请日：2013-11-22

Applicant: Broadcom Corporation

Inventor： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC: H01L21/50

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract translation: 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US20140087553A1

公开(公告)日：2014-03-27

申请号：US14087445

申请日：2013-11-22

Applicant: BROADCOM CORPORATION

Inventor： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract translation: 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分布层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US09390993B2

公开(公告)日：2016-07-12

申请号：US14518947

申请日：2014-10-20

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Galen Kirkpatrick ,  Edward Law ,  Reza Khan ,  Ming Wang Sze

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L23/3178 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/544 ,  H01L24/14 ,  H01L24/46 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

Abstract translation: 半导体封装包括包含有源电路层的半导体单元。 半导体封装还包括有源电路层上的多个接合焊盘，其被配置为连接到对应的外部导电连接器。 半导体封装还包括填充有源电路层的沟槽边缘的保护性密封剂涂层。 保护性密封剂涂层包含外部晶片单面。

公开(公告)号：US20160300661A1

公开(公告)日：2016-10-13

申请号：US14753482

申请日：2015-06-29

Applicant: Broadcom Corporation

Inventor： Namhoon Kim ,  Sampath Komarapalayam Karikalan ,  Zhihui Wang ,  Jin Seong Choi ,  Boon Leong Tan ,  Edward Law

IPC: H01F27/28 ,  H01F27/29

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F27/29 ,  H01F2027/2809

Abstract: Inductors are fabricated in core layers according to a predefined semiconductor package manufacturing process rules. The inductors provide an embedded substrate trace inductor solution. The inductors may be part of an on-chip voltage regulator or any other circuit design. The inductors provide a core spiral structure to help increase inductance, particularly using magnetic field coupling between inductors. The core layers provide thicker and heavier conductive segments for the inductors, particularly as compared to inductors fabricated in build-up layers according to the semiconductor package manufacturing process rules.

Abstract translation: 电感器根据预定义的半导体封装制造工艺规则在芯层中制造。 电感器提供嵌入式衬底跟踪电感器解决方案。 电感器可以是片上稳压器或任何其他电路设计的一部分。 电感器提供核心螺旋结构以帮助增加电感，特别是使用电感器之间的磁场耦合。 核心层为电感器提供较厚和较重的导电段，特别是与根据半导体封装制造工艺规则在积层中制造的电感器相比。

公开(公告)号：US20150303172A1

公开(公告)日：2015-10-22

申请号：US14263718

申请日：2014-04-28

Applicant: Broadcom Corporation

Inventor： Edward Law ,  Rezaur Rahman Khan ,  Kunzhong (Kevin) Hu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Reconstitution techniques for semiconductor packages are provided. One reconstitution technique is used to encapsulate a plurality of semiconductor packages into a single multi-chip module. Solder balls coupled to each package may be partially exposed after reconstitution, which enables the packages to be coupled to another device. Another reconstitution technique is used to couple a plurality of semiconductor packages into a package-on-package module using self-alignment feature(s). The self-alignment feature(s) are exposed solder ball(s) that are included in the bottom package of the package-on-package module. The exposed solder ball(s) serve as a frame of reference to other solder balls that are encapsulated by an encapsulation material. After the location of these other solders balls are determined, through-mold vias may be formed in the encapsulation material at locations corresponding to the other solder balls. The top package of the package-on-package module may then be coupled to the bottom package using these solder balls.

Abstract translation: 提供半导体封装的重构技术。 一种重构技术用于将多个半导体封装封装到单个多芯片模块中。 耦合到每个封装的焊球可以在重构之后被部分暴露，这使得封装能够耦合到另一个器件。 另一种重构技术用于使用自对准特征将多个半导体封装耦合到封装封装模块中。 自对准特征是包装在封装封装模块的底部封装中的暴露的焊球。 暴露的焊球作为被封装材料封装的其它焊球的参考框架。 在确定这些其它焊料球的位置之后，可以在封装材料中在与其它焊球相对应的位置处形成通孔模。 然后可以使用这些焊球将包装封装模块的顶部封装耦合到底部封装。

公开(公告)号：US09693461B2

公开(公告)日：2017-06-27

申请号：US14684256

申请日：2015-04-10

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Edward Law ,  Sampath Komarapalayam Karikalan ,  Neal Andrew Kistler ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01F5/00 ,  H05K1/18 ,  H01F17/00 ,  H01F41/04 ,  H01F27/28 ,  H01F17/04 ,  H01F38/14

CPC classification number: H05K1/181 ,  H01F17/0013 ,  H01F17/045 ,  H01F38/14 ,  H01F41/046 ,  H01F2017/0053 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L2224/16225

Abstract: A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

公开(公告)号：US20170011993A1

公开(公告)日：2017-01-12

申请号：US15205991

申请日：2016-07-08

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Sam Komarapalayam Karikalan ,  Edward Law ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/81

Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

Abstract translation: 提供半导体器件和制造方法，用于使用在活性半导体管芯和半导体衬底之间提供高密度界面的Recon插入件，并且还提供间距扇出。 例如，电路组件包括包括多个金属焊盘的硅焊盘层，每个金属焊盘被配置为接收多个凸块的相应凸块。 电路组件还包括设置在硅衬垫层上的氧化物层和设置在氧化物层上的介入层电介质层。 中介层介电层包括将再分布层的顶表面连接到插入层介电层的底表面的多个布线迹线。 电路组件还包括使用多个IC凸块和封装硅衬垫层的至少一部分的封装材料，在内插器电介质层的顶表面处附接到多个布线迹线的集成电路（IC）裸片， 氧化层，中介层介电层和IC芯片，为电路组件提供结构支撑。

公开(公告)号：US08922014B2

公开(公告)日：2014-12-30

申请号：US14086851

申请日：2013-11-21

Applicant: Broadcom Corporation

Inventor： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract translation: 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US20140210083A1

公开(公告)日：2014-07-31

申请号：US14229215

申请日：2014-03-28

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Reza-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

IPC: H01L23/00 ,  H01L23/12

CPC classification number: H01L24/48 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a device package is provided. The device package can include a substrate having first and second opposing surfaces, an opening being formed through the first and second surfaces of the substrate; a stiffener coupled to the first surface of the substrate, the stiffener having an extending portion that extends into the opening of the substrate; and an integrated circuit (IC) die coupled to the extending portion of the stiffener, the IC die being electrically coupled to the substrate.

Abstract translation: 在一个实施例中，提供了一种设备包。 器件封装可以包括具有第一和第二相对表面的衬底，通过衬底的第一和第二表面形成的开口; 加强件，其耦合到所述基板的所述第一表面，所述加强件具有延伸到所述基板的开口中的延伸部分; 以及耦合到所述加强件的所述延伸部分的集成电路（IC）管芯，所述IC管芯电耦合到所述衬底。

公开(公告)号：US20140084462A1

公开(公告)日：2014-03-27

申请号：US14086851

申请日：2013-11-21

Applicant: Broadcom Corporation

Inventor： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract translation: 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。