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23 条记录 (耗时 0.026 秒)

    Reduction of chip carrier flexing during thermal cycling
    5.
    发明授权
    Reduction of chip carrier flexing during thermal cycling 失效
    在热循环期间减少芯片载体弯曲

    公开(公告)号：US06818972B2

    公开(公告)日：2004-11-16

    申请号：US10262023

    申请日：2002-09-30

    申请人： Lisa J. Jimarez ,  Miguel A. Jimarez

    发明人： Lisa J. Jimarez ,  Miguel A. Jimarez

    IPC分类号： H01L23495

    CPC分类号： H01L23/49822 ,  B32B15/08 ,  H01L23/142 ,  H01L2224/16225 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/125 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present. Since a propensity for cracking of the stiff chip carrier increases as the thermally induced displacement increases, the present invention, which avoids use of the stiffener ring, improves a structural integrity of the chip carrier.

    摘要翻译： 用于减少热循环期间芯片载体弯曲的方法和结构。 半导体芯片耦合到刚性芯片载体（即具有至少约3×10 5 psi的弹性模量的芯片载体），并且在芯片载体的外围没有加强环。 没有加强环，芯片载体响应于由于芯片和芯片载体之间的热膨胀系数不匹配而引起热应变的温度变化，能够经受自然弯曲（与受限制的弯曲相反）。 如果芯片载体上的温度从室温变化到约-40℃的温度，如果加强环不存在，则芯片载体的表面的最大热诱导位移比如下 存在加强环。 由于热引起的位移增加，刚性芯片载体的开裂倾向增加，所以避免使用加强环的本发明改善了芯片载体的结构完整性。

    Z interconnect structure and method
    6.
    发明授权
    Z interconnect structure and method 失效
    Z互连结构和方法

    公开(公告)号：US06805280B2

    公开(公告)日：2004-10-19

    申请号：US10041261

    申请日：2002-01-08

    申请人： Lisa J. Jimarez ,  Mark V. Pierson

    发明人： Lisa J. Jimarez ,  Mark V. Pierson

    IPC分类号： B23K120

    CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/096

    摘要： The current invention provides a method of attaching a plurality of cores wherein a core has a via with a conductive surface to be electrically connected to a conductive surface on another core. The method provides for applying a metallurgical paste to a conductive surface, removing a portion of the flux from the paste and joining the two cores. The current invention also provides a structure including a plurality of cores wherein a metallurgical paste electrically connects a via with a conductive surface on a core to a conductive surface on another core.

    摘要翻译： 本发明提供了一种附接多个芯的方法，其中芯具有导电表面的通孔以电连接到另一芯上的导电表面。 该方法提供将冶金膏施加到导电表面，从糊料中去除一部分助熔剂并连接两个芯。 本发明还提供了一种包括多个芯的结构，其中冶金膏将通孔与芯上的导电表面电连接到另一芯上的导电表面。

    Z interconnect structure and method
    7.
    发明授权
    Z interconnect structure and method 有权
    Z互连结构和方法

    公开(公告)号：US07718902B2

    公开(公告)日：2010-05-18

    申请号：US10937654

    申请日：2004-09-09

    申请人： Lisa J. Jimarez ,  Mark V. Pierson

    发明人： Lisa J. Jimarez ,  Mark V. Pierson

    IPC分类号： H05K1/03

    CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/096

    摘要： The current invention provides a method of attaching a plurality of cores wherein a core has a via with a conductive surface to be electrically connected to a conductive surface on another core. The method provides for applying a metallurgical paste to a conductive surface, removing a portion of the flux from the paste and joining the two cores. The current invention also provides a structure including a plurality of cores wherein a metallurgical paste electrically connects a via with a conductive surface on a core to a conductive surface on another core.

    摘要翻译： 本发明提供了一种附接多个芯的方法，其中芯具有导电表面的通孔以电连接到另一芯上的导电表面。 该方法提供将冶金膏施加到导电表面，从糊料中去除一部分助熔剂并连接两个芯。 本发明还提供了一种包括多个芯的结构，其中冶金膏将通孔与芯上的导电表面电连接到另一芯上的导电表面。

    Method of forming a chip assembly
    10.
    发明授权
    Method of forming a chip assembly 失效
    形成芯片组件的方法

    公开(公告)号：US06757967B2

    公开(公告)日：2004-07-06

    申请号：US10119134

    申请日：2002-04-09

    申请人： Lisa J. Jimarez ,  Miguel A. Jimarez

    发明人： Lisa J. Jimarez ,  Miguel A. Jimarez

    IPC分类号： H05K330

    CPC分类号： H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

    摘要： A chip mounting assembly is provided which includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted ante substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed an the substrate. The stiffener member has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad. The invention also provides a method of forming such an I/C chip assembly.

    摘要翻译： 提供了一种芯片安装组件，其包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强构件，其被安装在前底座上并与集成电路芯片横向隔开。 至少一个导电接地焊盘形​​成为衬底。 加强件在其中具有至少一个通孔，并且导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。 本发明还提供了一种形成这种I / C芯片组件的方法。