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57 条记录 (耗时 0.027 秒)

    Application of a supercritical CO2 system for curing low k dielectric materials
    1.
    发明授权
    Application of a supercritical CO2 system for curing low k dielectric materials 失效
    应用超临界CO2系统固化低k电介质材料

    公开(公告)号：US06875709B2

    公开(公告)日：2005-04-05

    申请号：US10383710

    申请日：2003-03-07

    申请人： Chun-Hsien Lin ,  Henry Lo ,  Anthony Liu ,  Yu-Liang Lin

    发明人： Chun-Hsien Lin ,  Henry Lo ,  Anthony Liu ,  Yu-Liang Lin

    IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02134 ,  H01L21/02118 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02343 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/76826 ,  H01L21/76829

    摘要： A method and apparatus for curing and modifying a low k dielectric layer in an interconnect structure is disclosed. A spin-on low k dielectric layer which includes an organic silsesquioxane, polyarylether, bisbenzocyclobuene, or SiLK is spin coated on a substrate. The substrate is placed in a process chamber in a supercritical CO2 system and is treated at a temperature between 30° C. and 150° C. and at a pressure from 70 to 700 atmospheres. A co-solvent such as CF3—X or F—X is added that selectively replaces C—CH3 bonds with C—CF3 or C—F bonds. Alternatively, H2O2 is employed as co-solvent to replace a halogen in a C—Z bond where Z=F, Cl, or Br with an hydroxyl group. Two co-solvents may be combined with CO2 for more flexibility. The cured dielectric layer has improved properties that include better adhesion, lower k value, increased hardness, and a higher elastic modulus.

    摘要翻译： 公开了一种用于固化和修饰互连结构中的低k电介质层的方法和装置。 将包含有机倍半硅氧烷，聚芳醚，双苯并环丁烯或SiLK的旋涂低k电介质层旋涂在基材上。 将基材置于超临界CO 2体系的处理室中，并在30℃至150℃的温度和70至700大气压的压力下进行处理。 加入共溶剂如CF 3 -X或F-X，其选择性地用C-CF 3或C-F键取代C-CH 3键。 或者，使用H 2 O 2作为助溶剂代替C-Z键中的卤素，其中Z = F，Cl或Br与羟基。 两种共溶剂可以与二氧化碳组合以获得更大的灵活性。 固化的介电层具有改进的性能，其包括更好的附着力，较低的k值，更高的硬度和更高的弹性模量。

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    3.
    发明授权
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US07083495B2

    公开(公告)日：2006-08-01

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

    Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area
    5.
    发明授权
    Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area 失效
    解决对准标记盲目问题的方法和在微小区域应用半导体蚀刻技术

    公开(公告)号：US06746966B1

    公开(公告)日：2004-06-08

    申请号：US10353229

    申请日：2003-01-28

    申请人： Chung-Long Chang ,  Henry Lo ,  Shang-Ting Tsai ,  Yu-Liang Lin

    发明人： Chung-Long Chang ,  Henry Lo ,  Shang-Ting Tsai ,  Yu-Liang Lin

    IPC分类号： H01L21302

    CPC分类号： H01L21/31111 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084

    摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.

    摘要翻译： 一种解开对准标记的方法，包括以下步骤。 提供了在对准区域内具有单元区域和对准标记的基板。 在沟槽区内形成STI沟槽。 在衬底上形成氧化硅层，填充STI沟槽和对准标记。 将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。 湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。 剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。 还公开了一种滴蚀蚀刻装置。

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    8.
    发明申请
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US20050112997A1

    公开(公告)日：2005-05-26

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B37/04 ,  B24B51/00 ,  G05B13/02 ,  H01L21/3105 ,  H01L21/321 ,  B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。