公开(公告)号：US20070196011A1

公开(公告)日：2007-08-23

申请号：US11610468

申请日：2006-12-13

申请人： Damon Cox ,  Todd Egan ,  Randhir Thakur ,  Arkadii Samoilov ,  Per-Ove Hansson

发明人： Damon Cox ,  Todd Egan ,  Randhir Thakur ,  Arkadii Samoilov ,  Per-Ove Hansson

IPC分类号： H01L21/66 ,  G06K9/00

CPC分类号： G01N21/33 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67745

摘要： Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or pre-processing steps are performed on the substrate to provide data for processes performed on subsequent substrates. In one aspect of the invention, a system controller and one or more analysis devices are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.

摘要翻译： 本发明的方面通常提供一种使用多室处理系统来处理衬底的装置和方法，所述多室处理系统适于处理衬底并分析在衬底上执行的工艺的结果。 在本发明的一个方面，在衬底上执行一个或多个分析步骤和/或预处理步骤以提供在后续衬底上执行的处理的数据。 在本发明的一个方面，系统控制器和一个或多个分析装置用于监测和控制处理室配方和/或处理顺序，以减少由于所形成的装置中的缺陷和装置性能变异性问题引起的衬底废料。 本发明的实施例还通常提供了用于可重复且可靠地形成用于各种应用的半导体器件的方法和系统。

公开(公告)号：US20070134821A1

公开(公告)日：2007-06-14

申请号：US11460864

申请日：2006-07-28

申请人： Randhir Thakur ,  Arkadii Samoilov ,  Per-Ove Hansson

发明人： Randhir Thakur ,  Arkadii Samoilov ,  Per-Ove Hansson

IPC分类号： B08B6/00 ,  H01L21/00 ,  C23C16/00

CPC分类号： C23C16/4584 ,  B08B6/00 ,  B08B7/0057 ,  C23C16/45546 ,  C23C16/45593 ,  C23C16/481 ,  C23C16/54 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67757 ,  H01L21/67781

摘要： Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or precleaning steps are utilized to reduce the effect of queue time on device yield. In one aspect of the invention, a system controller and the one or more analysis chambers are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.

摘要翻译： 本发明的方面通常提供一种使用多室处理系统来处理衬底的装置和方法，所述多室处理系统适于处理衬底并分析在衬底上执行的工艺的结果。 在本发明的一个方面，利用一个或多个分析步骤和/或预清洗步骤来减少队列时间对设备产量的影响。 在本发明的一个方面，系统控制器和一个或多个分析室用于监测和控制处理室配方和/或处理顺序，以减少由于所形成的器件和器件性能变异性问题中的缺陷引起的衬底废料。 本发明的实施例还通常提供了用于可重复且可靠地形成用于各种应用的半导体器件的方法和系统。

公开(公告)号：US20060260538A1

公开(公告)日：2006-11-23

申请号：US11494903

申请日：2006-07-28

申请人： Zhiyuan Ye ,  Yihwan Kim ,  Xiaowei Li ,  Ali Zojaji ,  Nicholas Dalida ,  Jinsong Tang ,  Xiao Chen ,  Arkadii Samoilov

发明人： Zhiyuan Ye ,  Yihwan Kim ,  Xiaowei Li ,  Ali Zojaji ,  Nicholas Dalida ,  Jinsong Tang ,  Xiao Chen ,  Arkadii Samoilov

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

摘要： In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了在基板上形成外延膜的方法。 该方法包括（a）提供衬底; （b）将衬底暴露于硅源和碳源以形成含碳硅外延膜; （c）用封装膜封装含碳硅外延膜; 和（d）将衬底暴露于Cl2以蚀刻封装膜。 提供了许多其他方面。

公开(公告)号：US20060234488A1

公开(公告)日：2006-10-19

申请号：US11420906

申请日：2006-05-30

申请人： Yihwan Kim ,  Arkadii Samoilov

发明人： Yihwan Kim ,  Arkadii Samoilov

IPC分类号： H01L21/44

CPC分类号： H01L21/0237 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78 ,  H01L29/7848

摘要： The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in the range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment teaches a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods may include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

摘要翻译： 本发明通常教导了一种在衬底上沉积硅膜或硅锗膜的方法，包括将衬底放置在处理室内并将衬底表面加热至约600℃至约900℃的温度，同时 保持在约0.1托至约200托的范围内的压力。 沉积气体被提供到处理室，并且包括SiH 4 Si，可选的锗源气体，蚀刻剂，载气和任选的至少一种掺杂剂气体。 在基板上选择性地并外延生长硅膜或硅锗膜。 一个实施方案教导了用惰性气体作为载气沉积含硅膜的方法。 方法可以包括使用选择性硅锗外延膜的电子器件的制造。

公开(公告)号：US20060169668A1

公开(公告)日：2006-08-03

申请号：US11047323

申请日：2005-01-31

申请人： Arkadii Samoilov

发明人： Arkadii Samoilov

IPC分类号： B44C1/22 ,  B08B6/00 ,  H01L21/311 ,  C23F1/00 ,  C25F1/00 ,  C25F5/00

CPC分类号： H01L21/02019 ,  B08B7/0035 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3065 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814

摘要： In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about 100 Å/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. The silicon-containing surface is exposed to an etching gas that contains an etchant, preferably chlorine, a carrier gas and an optional silicon source.

摘要翻译： 在本发明的一个实施方案中，提供了一种用于整理或处理含硅表面的方法，其包括通过缓蚀刻工艺（例如，约/ 100 / min）去除污染物和/或平滑表面上所含的表面。 含硅表面暴露于含有蚀刻剂，硅源和载气的蚀刻气体。 优选地，蚀刻剂是氯气，使得在蚀刻或平滑处理期间使用相对低的温度（例如<800℃）。 在本发明的另一个实施例中，提供了一种用于在快速蚀刻工艺（例如，约> 100 / min）期间蚀刻含硅表面的方法，其包括去除含硅材料以在源极/漏极中形成凹陷 S / D）面积。 含硅表面暴露于含有蚀刻剂，优选氯，载气和任选的硅源的蚀刻气体。

公开(公告)号：US20050079691A1

公开(公告)日：2005-04-14

申请号：US10683937

申请日：2003-10-10

申请人： Yihwan Kim ,  Arkadii Samoilov

发明人： Yihwan Kim ,  Arkadii Samoilov

IPC分类号： H01L21/20 ,  H01L21/205

CPC分类号： H01L21/0237 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78 ,  H01L29/7848

摘要： The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in the range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment teaches a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods may include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

摘要翻译： 本发明通常教导了一种在衬底上沉积硅膜或硅锗膜的方法，包括将衬底放置在处理室内并将衬底表面加热至约600℃至约900℃的温度，同时 保持在约0.1托至约200托的范围内的压力。 沉积气体被提供到处理室，并且包括SiH 4，可选的锗源气体，蚀刻剂，载气和任选的至少一种掺杂气体。 在基板上选择性地并外延生长硅膜或硅锗膜。 一个实施方案教导了用惰性气体作为载气沉积含硅膜的方法。 方法可以包括使用选择性硅锗外延膜的电子器件的制造。

公开(公告)号：US08643150B1

公开(公告)日：2014-02-04

申请号：US13396804

申请日：2012-02-15

申请人： Yong L. Xu ,  Viren Khandekar ,  Yi-Sheng A. Sun ,  Arkadii Samoilov

发明人： Yong L. Xu ,  Viren Khandekar ,  Yi-Sheng A. Sun ,  Arkadii Samoilov

IPC分类号： H01L23/58

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05172 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2224/05552

摘要： Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

摘要翻译： 描述了晶片级封装（半导体）器件，其具有至少部分地延伸到焊料凸块中以减轻对焊料凸块的热应力的柱结构。 在实现中，晶片级封装器件可以包括具有设置在表面上的表面和焊料凸块的集成电路芯片。 晶片级封装器件还可以包括设置在表面上的至少部分地延伸到焊料凸块中的柱结构。

公开(公告)号：US08575493B1

公开(公告)日：2013-11-05

申请号：US13033675

申请日：2011-02-24

申请人： Yong Li Xu ,  Duane Thomas Wilcoxen ,  Yi-Sheng Sun ,  Viren Khandekar ,  Arkadii Samoilov

发明人： Yong Li Xu ,  Duane Thomas Wilcoxen ,  Yi-Sheng Sun ,  Viren Khandekar ,  Arkadii Samoilov

IPC分类号： H05K1/03

CPC分类号： H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

摘要： Semiconductor devices are described that have an extended under ball metallization configured to mitigate dielectric layer cracking due to stress, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests, or cyclic bending tests, and so on. In an implementation, the semiconductor package devices include an integrated circuit chip having a solder ball and under ball metallization, formed on the integrated circuit chip, which is configured to receive the solder ball so that the solder ball and the under ball metallization have a contact area there between, wherein the area of the under ball metallization is area greater than the contact area.

公开(公告)号：US08492284B2

公开(公告)日：2013-07-23

申请号：US13305235

申请日：2011-11-28

申请人： Arkadii Samoilov

发明人： Arkadii Samoilov

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02019 ,  B08B7/0035 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3065 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814

摘要： Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 Å per minute to about 20 Å per minute during the etching process.

摘要翻译： 实施例提供了在衬底上蚀刻和沉积硅材料的方法。 在一个实例中，该方法包括将包含含硅材料的基材加热至约800℃或更低的温度，并且除去一部分含硅材料和污染物以露出含硅材料的暴露表面 在沉积过程期间，在含硅材料的暴露表面上沉积含硅层。 该方法进一步提供了在同一个室内进行蚀刻和沉积工艺，并且在蚀刻和沉积工艺期间利用氯气和硅源气体。 在一些实例中，在蚀刻过程中，以每分钟约2埃至每分钟约20埃的速率除去含硅材料。

公开(公告)号：US08264089B2

公开(公告)日：2012-09-11

申请号：US12725967

申请日：2010-03-17

申请人： Rey Alvarado ,  Tie Wang ,  Arkadii Samoilov

发明人： Rey Alvarado ,  Tie Wang ,  Arkadii Samoilov

IPC分类号： H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05541 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/11424 ,  H01L2224/11602 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2224/11 ,  H01L2924/207 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

摘要翻译： WLP器件在铜柱式电路连接的顶部设置有凸缘形UBM或嵌入式部分焊球UBM。