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1.发明授权Reduced electromigration and stressed induced migration of copper wires by surface coating 有权通过表面涂层减少电迁移和应力诱导的铜线迁移公开(公告)号：US07468320B2
公开(公告)日：2008-12-23
申请号：US11183773
申请日：2005-07-19
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76864 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.
摘要翻译： 本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。 该涂层足够薄，以便消除对通过抛光进行附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已经被本发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热 压力消除。 此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。 自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。 提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。 尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。
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2.发明授权Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond 有权用于制造铜C4和引线键的自对准防腐蚀工艺公开(公告)号：US06457234B1
公开(公告)日：2002-10-01
申请号：US09311973
申请日：1999-05-14
IPC分类号： H01R900
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.
摘要翻译： 用于在衬底上制造耐腐蚀导电焊盘的自对准（即，空间选择性）工艺以及包括允许端子连接到导电焊盘的互连的相关结构（例如，芯片到封装的连接 ）。 导电焊盘可以包括诸如铜，铝或钨的金属。 自对准工艺在初始暴露的金属层上产生金属层，其中金属层是导电的和耐腐蚀的。 该方法可以通过提供具有暴露表面的金属层的基底，在暴露的表面上沉积第二金属层，退火基底以使包含暴露表面的金属层的一部分和第二金属层的一部分 金属层，并且去除第二金属层的非合金部分。
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公开(公告)号：US06779711B2
公开(公告)日：2004-08-24
申请号：US10180777
申请日：2002-06-25
IPC分类号： B23K120
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.
摘要翻译： 用于在衬底上制造耐腐蚀导电焊盘的自对准工艺，以及包括允许端子与焊盘连接的互连的结构。 该工艺在初始暴露的金属层上产生金属层。 金属层具有导电性和耐腐蚀性。 该方法包括提供具有暴露表面的金属层的基底，在暴露表面上沉积第二金属层，退火基底以合金包含暴露表面的金属层的一部分和第二金属层的一部分， 以及去除所述第二金属层的非合金部分。 替代方法包括在基底上提供金属层，以及在金属层上无电镀镀耐腐蚀金属或合金。 替代方法可以另外包括在抗腐蚀金属或合金上无电镀第二耐腐蚀金属。
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公开(公告)号：US07081680B2
公开(公告)日：2006-07-25
申请号：US10849459
申请日：2004-05-19
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.
摘要翻译： 包括衬底和互连的电结构。 衬底包括在金属层上的导电且耐腐蚀的金属层。 互连电耦合到金属层。 金属层的顶表面位于衬底的顶表面之上，并且金属层的底表面与金属层的顶表面的第一部分直接机械接触。 金属层是非合金的并且包括金属。
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公开(公告)号：US06503834B1
公开(公告)日：2003-01-07
申请号：US09677585
申请日：2000-10-03
申请人： Xiaomeng Chen , Mahadevaiyer Krishnan , Judith M. Rubino , Carlos J. Sambucetti , Soon-Cheon Seo , James A. Tornello
发明人： Xiaomeng Chen , Mahadevaiyer Krishnan , Judith M. Rubino , Carlos J. Sambucetti , Soon-Cheon Seo , James A. Tornello
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/288
摘要： The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.
摘要翻译： 本发明提供了增加BEOL互连的可靠性的过程。 该方法包括在晶片衬底上的电介质层上形成导体阵列，抛光上表面，使得导体的表面与电介质层的上表面基本上共面，在上表面上形成合金膜 的导体，并刷清洁导体和电介质层的上表面。
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公开(公告)号：US06656750B1
公开(公告)日：2003-12-02
申请号：US09301889
申请日：1999-04-29
IPC分类号： G01R3126
CPC分类号： H01L24/13 , B23K1/0016 , B23K1/20 , B23K2101/36 , G01R31/2886 , H01L22/00 , H01L24/11 , H01L24/14 , H01L2224/0401 , H01L2224/0603 , H01L2224/1148 , H01L2224/1184 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/14051 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H01L2924/00014
摘要： A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.
摘要翻译： 公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。 在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。 因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。 探针可以容易地进行，凸块的所有Z高度基本相等。 焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块 呈短圆柱形。 当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。
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公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。
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8.发明授权Method for preparing a conductive pad for electrical connection and conductive pad formed 有权制备用于电连接的导电焊盘和形成的导电焊盘的方法公开(公告)号：US06335104B1
公开(公告)日：2002-01-01
申请号：US09510996
申请日：2000-02-22
申请人： Carlos J. Sambucetti , Daniel C. Edelstein , John G. Gaudiello , Judith M. Rubino , George Walker
发明人： Carlos J. Sambucetti , Daniel C. Edelstein , John G. Gaudiello , Judith M. Rubino , George Walker
IPC分类号： B32B1500
CPC分类号： H01L24/48 , C23C18/1608 , C23C18/1651 , C23C18/1831 , C23C18/1844 , C23C18/34 , C23C18/36 , C23C18/54 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05082 , H01L2224/05147 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13099 , H01L2224/13111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48799 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/48869 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H05K3/244 , H05K13/06 , Y10S428/926 , Y10S428/936 , Y10T428/12493 , Y10T428/12646 , Y10T428/12674 , Y10T428/12771 , Y10T428/12778 , Y10T428/12875 , Y10T428/12889 , Y10T428/12896 , Y10T428/12903 , Y10T428/1291 , Y10T428/12944 , Y10T428/12986 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2924/00015
摘要： A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.
摘要翻译： 提供了一种制备具有优异的扩散阻挡层和粘合性能的用于电连接的铜焊盘表面的方法。 在该方法中，首先提供已经被酸溶液清洗的铜焊盘表面，然后在铜焊盘表面上沉积磷或含硼金属合金的保护层，然后将贵金属的粘附层 沉积在保护层的顶部。 保护层可以是由磷或含硼金属合金如Ni-P，Co-P，Co-WP，Co-Sn-P，Ni-WP紧密连接在一起的两层或更多层 ，Co-B，Ni-B，Co-Sn-B，Co-WB和Ni-WB，厚度在约至Å至约Å之间。 粘合层可以由贵金属如Au，Pt，Pd和Ag形成，厚度在约至约4,000之间。
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公开(公告)号：US07033648B1
公开(公告)日：2006-04-25
申请号：US08781926
申请日：1996-12-30
CPC分类号： C23C18/22 , C23C18/1605 , C23C18/1641 , C23C18/1692 , C23C18/2006 , C23C18/208 , C23C18/30 , C23C18/31 , H05K1/0346 , H05K3/0032 , H05K3/184 , H05K3/381 , H05K2203/0793 , H05K2203/083 , H05K2203/095
摘要： A method to selectively metallize polyimide with an all-electroless process.
摘要翻译： 选择性地使全化学镀金属化聚酰亚胺的方法。
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公开(公告)号：US06197222B1
公开(公告)日：2001-03-06
申请号：US09119569
申请日：1998-07-20
申请人： Ravi F. Saraf , Judith Marie Roldan , Michael Anthony Gaynes , Richard Benton Booth , Steven Paul Ostrander , Emanuel I. Cooper , Carlos J. Sambucetti
发明人： Ravi F. Saraf , Judith Marie Roldan , Michael Anthony Gaynes , Richard Benton Booth , Steven Paul Ostrander , Emanuel I. Cooper , Carlos J. Sambucetti
IPC分类号： H01B104
CPC分类号： H01L24/81 , H01B1/22 , H01L23/49883 , H01L2224/13009 , H01L2224/81801 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/321 , H05K3/4614 , H05K3/4632 , H05K2201/0129 , H05K2201/0133 , H05K2201/0162 , H05K2203/0783
摘要： An electrically conductive paste which includes a thermoplastic polymer, a conductive metal powder and an organic solvent system is disclosed. The invention further encompasses an electrically conductive composite which includes the aforementioned thermoplastic and metal, wherein the metal represents at least about 30% by volume, based on the total volume of the composite. The composite is formed from the paste under elevated temperature. The paste is employed in processes which involve electrically connecting electrical and electronic components under process conditions which convert the paste to the composite.
摘要翻译： 公开了一种包括热塑性聚合物，导电金属粉末和有机溶剂系统的导电浆料。 本发明还包括一种包含上述热塑性和金属的导电复合材料，其中基于复合材料的总体积，金属占体积的至少约30体积％。 复合材料由高温下的糊料形成。 该糊剂用于涉及将糊料转化为复合材料的工艺条件下的电气和电子部件电连接的工艺。
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