公开(公告)号：US20070029674A1

公开(公告)日：2007-02-08

申请号：US11375760

申请日：2006-03-14

申请人： Dong-Kil Shin ,  Se-Young Yang ,  Shin Kim ,  Wang-Ju Lee

发明人： Dong-Kil Shin ,  Se-Young Yang ,  Shin Kim ,  Wang-Ju Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3157 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is a board-on-chip package and stack package using the same to reduce the likelihood that bonding wires in an encapsulant may be damaged due to mechanical stresses applied during a package stacking process. A semiconductor package may have a spacer provided along the opposing sides of an encapsulant. The spacer may be spaced away from bonding wires embedded in the encapsulant. The height of the spacer may be greater than the height of the encapsulated bonding wire from the bottom surface of the semiconductor package. The spacer may be formed of a bar or a protrusion. In a stack package using the semiconductor package, the spacer may be provided between a semiconductor chip of a lower semiconductor package and an encapsulant of an upper semiconductor package.

摘要翻译： 提供了一种使用其的片上封装和堆叠封装，以减少由于在封装堆叠过程中施加的机械应力而使密封剂中的接合线可能被损坏的可能性。 半导体封装可以具有沿密封剂的相对侧设置的间隔件。 间隔件可以与嵌入密封剂中的接合线间隔开。 间隔件的高度可以大于封装的接合线从半导体封装的底表面的高度。 间隔件可以由杆或突起形成。 在使用半导体封装的堆叠封装中，间隔件可以设置在下半导体封装的半导体芯片和上半导体封装的封装件之间。

公开(公告)号：US20100230811A1

公开(公告)日：2010-09-16

申请号：US12722794

申请日：2010-03-12

申请人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC分类号： H01L23/498

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

摘要翻译： 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US06638638B2

公开(公告)日：2003-10-28

申请号：US09954026

申请日：2001-09-18

申请人： Sang-Young Kim ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Seung-Kon Mok

发明人： Sang-Young Kim ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Seung-Kon Mok

IPC分类号： B22F300

CPC分类号： H01L24/10 ,  B23K1/0008 ,  B23K35/0222 ,  B23K35/0244 ,  B23K2101/40 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10257 ,  H05K2203/0465 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/12014 ,  Y10T428/12222 ,  H01L2224/29099 ,  H01L2924/00

摘要： A solder structure comprising a radially-curved exterior surface enclosing a predetermined-sized cavity used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an annular conductive pad and the other planar element having either a corresponding annular or circular conductive pad, separated by a spherical solder compound comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

摘要翻译： 焊料结构包括径向弯曲的外表面，其包围预定尺寸的空腔，用于在预定的导电接触点处柔性地接合两个具有不同性质的平面元件。 通过以分层布置组装两个平面元件，一个平面元件具有环形导电焊盘，另一个平面元件具有相应的环形或圆形导电焊盘，由由焊料和助熔剂构成的球形焊料化合物分开， 可以在焊料化合物的熔化和随后的冷却期间产生焊料结构。 所得中空焊料结构的可塑性/弹性特性吸收两个平面元件相对于彼此的横向移动，而不会降低焊接接头。

公开(公告)号：US20110079897A1

公开(公告)日：2011-04-07

申请号：US12894540

申请日：2010-09-30

申请人： Jin-Woo PARK ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

发明人： Jin-Woo PARK ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

摘要翻译： 在集成电路（IC）芯片和具有其的倒装芯片封装中，不设置布线，并且第一电极焊盘不与IC芯片的焊盘区域中的布线接触。 因此，与焊盘区域中的布线无关，第一凸块结构与第一电极接触。 第二电极焊盘与IC芯片的伪焊盘区域中的布线接触。 因此，伪焊盘区域中的第二凸块结构在与第二电极下方的布线间隔开的接触点处与第二电极的上表面接触。

公开(公告)号：US20100259912A1

公开(公告)日：2010-10-14

申请号：US12662218

申请日：2010-04-06

申请人： Dong-Kil Shin ,  Shle-Ge Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee

IPC分类号： H05K1/11

CPC分类号： H05K1/111 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  Y02P70/611 ,  Y02P70/613

摘要： Provided is an electronic device which may include a first structure having a first surface, a first land region on the first surface, a second structure having a second surface facing the first surface, a second land region on the second surface, and a connection structure between the first and second structures electrically connecting the first land region to the second land region. As provided, the first land region may have a major axis and a minor axis on the first surface and the second land region may have a major axis and a minor axis on the second surface. Furthermore, the major axes of the first and second land regions may have different orientations with respect to one another.

摘要翻译： 提供一种电子设备，其可以包括第一结构，其具有第一表面，第一表面上的第一焊盘区域，具有面向第一表面的第二表面的第二结构，第二表面上的第二焊盘区域，以及连接结构 在第一和第二结构之间，电连接第一焊盘区域和第二焊盘区域。 如上所述，第一焊盘区域可以在第一表面上具有长轴和短轴，并且第二焊盘区域可以在第二表面上具有长轴和短轴。 此外，第一和第二脊区域的长轴可以具有彼此不同的取向。

公开(公告)号：US08922012B2

公开(公告)日：2014-12-30

申请号：US12894540

申请日：2010-09-30

申请人： Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

发明人： Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

摘要翻译： 在集成电路（IC）芯片和具有其的倒装芯片封装中，不设置布线，并且第一电极焊盘不与IC芯片的焊盘区域中的布线接触。 因此，与焊盘区域中的布线无关，第一凸块结构与第一电极接触。 第二电极焊盘与IC芯片的伪焊盘区域中的布线接触。 因此，伪焊盘区域中的第二凸块结构在与第二电极下方的布线间隔开的接触点处与第二电极的上表面接触。

公开(公告)号：US08120176B2

公开(公告)日：2012-02-21

申请号：US12722794

申请日：2010-03-12

申请人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

摘要翻译： 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US06756668B2

公开(公告)日：2004-06-29

申请号：US10232344

申请日：2002-08-30

申请人： Joong-Hyun Baek ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Yun-Hyeok Im

发明人： Joong-Hyun Baek ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Yun-Hyeok Im

IPC分类号： H01L2312

CPC分类号： H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

公开(公告)号：US08427841B2

公开(公告)日：2013-04-23

申请号：US12662218

申请日：2010-04-06

申请人： Dong-Kil Shin ,  Shle-Ge Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee

IPC分类号： H05K7/00

CPC分类号： H05K1/111 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  Y02P70/611 ,  Y02P70/613

摘要： Provided is an electronic device which may include a first structure having a first surface, a first land region on the first surface, a second structure having a second surface facing the first surface, a second land region on the second surface, and a connection structure between the first and second structures electrically connecting the first land region to the second land region. As provided, the first land region may have a major axis and a minor axis on the first surface and the second land region may have a major axis and a minor axis on the second surface. Furthermore, the major axes of the first and second land regions may have different orientations with respect to one another.

摘要翻译： 提供一种电子设备，其可以包括第一结构，其具有第一表面，第一表面上的第一焊盘区域，具有面向第一表面的第二表面的第二结构，第二表面上的第二焊盘区域，以及连接结构 在第一和第二结构之间，电连接第一焊盘区域和第二焊盘区域。 如上所述，第一焊盘区域可以在第一表面上具有长轴和短轴，并且第二焊盘区域可以在第二表面上具有长轴和短轴。 此外，第一和第二脊区域的长轴可以具有彼此不同的取向。

公开(公告)号：US20080122056A1

公开(公告)日：2008-05-29

申请号：US11983451

申请日：2007-11-09

申请人： Shle-Ge Lee ,  Dong-Kil Shin ,  Min-Young Son

发明人： Shle-Ge Lee ,  Dong-Kil Shin ,  Min-Young Son

IPC分类号： H01L23/488

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is a semiconductor device package comprising a printed circuit board, the printed circuit board including a window at a central portion and a connection part, a semiconductor chip including center-type bonding pads, wherein the semiconductor chip is mounted on an upper surface of the printed circuit board such that the center-type bonding pads are exposed by the window, bonding wires electrically connecting the center-type bonding pads with the printed circuit board through the window, a lower molding material at a lower surface of the printed circuit board, the lower molding material encapsulating the center-type bonding pads and the bonding wires, and an upper molding material encapsulating the semiconductor chip and the upper surface of the printed circuit board, wherein the lower molding material and the upper molding material are connected to each other through the connection part of the printed circuit board.

摘要翻译： 提供一种半导体器件封装，其包括印刷电路板，印刷电路板包括在中心部分处的窗口和连接部分，包括中心型接合焊盘的半导体芯片，其中半导体芯片安装在 印刷电路板，使得中心型接合焊盘由窗户露出，通过窗口将中心型接合焊盘与印刷电路板电连接的接合线，印刷电路板的下表面处的下部成型材料， 封装中心型接合焊盘和接合线的下部成型材料以及封装半导体芯片和印刷电路板的上表面的上部成型材料，其中下部成型材料和上部成型材料彼此连接 通过印刷电路板的连接部分。