公开(公告)号：US06905589B2

公开(公告)日：2005-06-14

申请号：US10370529

申请日：2003-02-24

申请人： Frank D. Egitto ,  Voya P. Markovich ,  Thomas R. Miller

发明人： Frank D. Egitto ,  Voya P. Markovich ,  Thomas R. Miller

IPC分类号： H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  C25D5/02

CPC分类号： H05K3/4644 ,  H05K1/112 ,  H05K3/423 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/0733

摘要： A method of making a circuitized substrate in which a commoning layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a printed circuit board or the like. The structure, including such a chip and circuit board is ideally suited for use within an information handling system.

摘要翻译： 一种制造电路化基板的方法，其中共用层在诸如用于将芯片耦合到印刷电路板等的层叠插入件的多层部件中形成多个基本上垂直排列的导电开口。 包括这种芯片和电路板的结构非常适合在信息处理系统中使用。

公开(公告)号：US06790305B2

公开(公告)日：2004-09-14

申请号：US10266652

申请日：2002-10-08

申请人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

发明人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

IPC分类号： B32B3114

CPC分类号： H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

摘要： A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

摘要翻译： 一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。 一种用于平行制造中间结构的方法，其随后连接以形成最终结构。 此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

公开(公告)号：US06955849B2

公开(公告)日：2005-10-18

申请号：US10854598

申请日：2004-05-26

申请人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

发明人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

IPC分类号： H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B7/12

CPC分类号： H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

摘要： A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

摘要翻译： 一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。 一种用于平行制造中间结构的方法，其随后连接以形成最终结构。 此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

公开(公告)号：US07083901B2

公开(公告)日：2006-08-01

申请号：US10262724

申请日：2002-10-01

申请人： Frank D. Egitto ,  Voya Markovich ,  Thomas R. Miller ,  Douglas O. Powell ,  James R. Wilcox

发明人： Frank D. Egitto ,  Voya Markovich ,  Thomas R. Miller ,  Douglas O. Powell ,  James R. Wilcox

IPC分类号： G03C5/00 ,  H01K3/00

CPC分类号： H05K3/4069 ,  H05K3/062 ,  H05K3/108 ,  H05K3/423 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4614 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09554 ,  H05K2203/025 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49179

摘要： A layer for use in a modular assemblage for supporting ICES is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.

摘要翻译： 用于支撑ICES的模块化组件中的层由用于组装的金属触点形成，通过在两层电介质之间制造金属互连构件的夹层; 通过电介质钻孔，停止在与模块底面接合的金属层上; 形成在所述互连构件上停止的盲孔; 并通过通孔的体积电镀金属孔，这两个孔都是盲孔，从而在堆叠形成复杂互连组件的层中形成垂直和水平连接。

公开(公告)号：US09351408B2

公开(公告)日：2016-05-24

申请号：US12764997

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/09 ,  H05K1/03 ,  H05K3/40

CPC分类号： H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K2203/063

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US08536459B2

公开(公告)日：2013-09-17

申请号：US12764994

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/03 ,  H05K1/02 ,  H05K1/09

CPC分类号： H05K3/4623 ,  H05K1/092 ,  H05K3/4053 ,  H05K3/4614 ,  H05K3/4691 ,  H05K2203/061

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US07875811B2

公开(公告)日：2011-01-25

申请号：US12010335

申请日：2008-01-24

申请人： David V. Caletka ,  Frank D. Egitto

发明人： David V. Caletka ,  Frank D. Egitto

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US20080217050A1

公开(公告)日：2008-09-11

申请号：US11873435

申请日：2007-10-17

申请人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

发明人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC分类号： H01R12/04 ,  B29C65/48

CPC分类号： H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

摘要翻译： 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US20080142258A1

公开(公告)日：2008-06-19

申请号：US12010335

申请日：2008-01-24

申请人： David V, Caletka ,  Frank D. Egitto

发明人： David V, Caletka ,  Frank D. Egitto

IPC分类号： H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。