公开(公告)号：US6072211A

公开(公告)日：2000-06-06

申请号：US128022

申请日：1998-08-03

Applicant: Gerald R. Miller ,  Lakshminarayan Viswanathan ,  Alan D. Wood

Inventor： Gerald R. Miller ,  Lakshminarayan Viswanathan ,  Alan D. Wood

IPC: H01L23/64 ,  H01L23/66 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L23/66 ,  H01L23/642 ,  H01L23/645 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111

Abstract: A semiconductor package (10) forms an impedance matching capacitor by utilizing an insulator (12), a conductor (19) on the dielectric, and a substrate (11) as elements of the capacitor. The capacitor is electrically connected, as part of an impedance matching network to shunt the inductance of the bonding wires (21) that connect the semiconductor die (18) an input lead (17).

Abstract translation: 半导体封装（10）通过利用绝缘体（12），电介质上的导体（19）和作为电容器的元件的衬底（11）形成阻抗匹配电容器。 电容器电连接，作为阻抗匹配网络的一部分，以分流连接半导体管芯（18）和输入引线（17）的接合线（21）的电感。

公开(公告)号：US06261868B1

公开(公告)日：2001-07-17

申请号：US09285827

申请日：1999-04-02

Applicant: Gerald R. Miller ,  Lakshminarayan Viswanathan

Inventor： Gerald R. Miller ,  Lakshminarayan Viswanathan

IPC: H01L2144

CPC classification number: H01L23/66 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/00

Abstract: A method for packaging a semiconductor device (23) to form a semiconductor component (10). A die attach material (17) is disposed on a flange (11). A semiconductor chip (23) is bonded to the die attach material (17). After disposing the die attach material (17) on the flange (11), an insulator material (28) is coupled to the flange (11). A leadframe (32) is coupled to the semiconductor chip (23) via a plurality of wirebonds (36). The wirebonds (36) and the semiconductor chip (23) are protected by a lid (37).

Abstract translation: 一种用于封装半导体器件（23）以形成半导体部件（10）的方法。 芯片附接材料（17）设置在凸缘（11）上。 半导体芯片（23）被接合到管芯附着材料（17）上。 在将管芯附着材料（17）设置在凸缘（11）上之后，绝缘体材料（28）联接到凸缘（11）上。 引线框架（32）经由多个引线键（36）耦合到半导体芯片（23）。 线圈（36）和半导体芯片（23）由盖（37）保护。

公开(公告)号：US06072238A

公开(公告)日：2000-06-06

申请号：US287282

申请日：1999-04-07

Applicant: Lakshminarayan Viswanathan ,  David F. Abdo ,  Gerald R. Miller

Inventor： Lakshminarayan Viswanathan ,  David F. Abdo ,  Gerald R. Miller

IPC: H01L23/66 ,  H01L23/34

CPC classification number: H01L23/66 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/30111

Abstract: A semiconductor device (10) suitable for use in RF applications and a method of forming the semiconductor device (10). An RF transistor die (31) is bonded to a heatsink (21). The heatsink (21) having the semiconductor chip (31) mounted thereto is coupled to a printed circuit board (11), wherein the RF transistor die (31) extends through an opening (14) in the printed circuit board (11). Conductors (18, 19) on the printed circuit board (11) are coupled to the semiconductor chip (31) via wirebonds (35, 36).

Abstract translation: 适用于RF应用的半导体器件（10）和形成半导体器件（10）的方法。 RF晶体管管芯（31）与散热片（21）接合。 安装有半导体芯片（31）的散热器（21）耦合到印刷电路板（11），其中RF晶体管管芯（31）延伸穿过印刷电路板（11）中的开口（14）。 印刷电路板（11）上的导体（18,19）经由引线键（35,36）耦合到半导体芯片（31）。

公开(公告)号：US09538659B2

公开(公告)日：2017-01-03

申请号：US13972838

申请日：2013-08-21

Applicant: Lakshminarayan Viswanathan ,  Jaynal A. Molla ,  Mahesh K. Shah

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla ,  Mahesh K. Shah

IPC: H01R9/00 ,  H05K1/18 ,  B23K1/20 ,  H05K1/14 ,  H05K1/05

CPC classification number: H05K1/181 ,  B23K1/20 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/056 ,  H05K1/141 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10416 ,  H05K2201/10553 ,  H05K2203/1173 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T428/12389 ,  H01L2924/00014

Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.

Abstract translation: 焊料可润湿凸缘的实施例包括由导电材料形成的凸缘体。 凸缘体具有底表面，顶表面，在顶表面和底表面之间延伸的侧壁以及从底表面延伸到凸缘体中的一个或多个凹陷。 每个凹陷由凹陷表面限定，凹陷表面可以或可以不是可焊料润湿的。 在将凸缘焊接到基板期间，凹陷可以用作多余焊料的储存器。 实施例还包括包括这种焊料可润湿凸缘的装置和系统，以及用于形成焊料可润湿凸缘，装置和系统的方法。

公开(公告)号：US09466588B2

公开(公告)日：2016-10-11

申请号：US14628766

申请日：2015-02-23

Applicant: Fernando A. Santos ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

Inventor： Fernando A. Santos ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/367 ,  H01L23/433 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49579 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85801 ,  H01L2224/8584 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20755 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.

Abstract translation: 封装的半导体器件可以包括安装到引线框的引线框架和管芯载体。 模具载体由导电和导热材料形成。 模具安装到模具载体的表面，其模头附着材料具有超过240℃的熔点。方法可以包括提供模具载体，在超过240℃的温度下熔融模具附着材料。 将模具附接到模具载体的表面以形成子组件，将子组件附接到引线框架，将模具和引线框架电互连，并且封装模具和引线框架的至少一部分以形成封装 设备。

公开(公告)号：US09159588B2

公开(公告)日：2015-10-13

申请号：US14204338

申请日：2014-03-11

Applicant: Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

Inventor： Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L21/768 ,  H01L23/495

CPC classification number: H01L21/56 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20755 ,  H01L2924/00012

Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.

Abstract translation: 一种包装无铅半导体器件的方法，其包括使用高温管芯附接工艺将半导体管芯耦合到其上的散热器法兰。 半导体器件还包括预先形成有弯曲的端子焊盘的框架结构。 框架结构与凸缘组合，使得凸缘的下表面和每个端子衬垫的下部共同对准，并且使得每个端子衬垫的上部部分覆盖凸缘。 互连器件将管芯与端子焊盘的上部部分互连。 密封剂将框架结构，法兰，管芯和每个端子衬垫的下部和凸缘的下表面保持暴露于密封剂的相互连接。

公开(公告)号：US20140022020A1

公开(公告)日：2014-01-23

申请号：US13554034

申请日：2012-07-20

Applicant: Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

Inventor： Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

IPC: H01L23/60 ,  H03F3/68

CPC classification number: H01L23/5227 ,  H01L23/293 ,  H01L23/49506 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2224/49175 ,  H01L2924/3011 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/245 ,  H01L2924/00

Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.

Abstract translation: 提供了减少在封装内体现的半导体器件的元件之间的电磁耦合的单个半导体器件封装。 对于诸如Doherty功率放大器的双通道放大器，将载波放大器元件与峰值放大器元件分离的隔离特征包括在半导体器件封装内。 隔离特征可以采取由耦合到地并且分离放大器的元件的导电材料构成的结构的形式。 隔离特征可以包括在各种半导体封装中，包括气腔封装和包覆成型的封装。 通过使用由本发明的实施例提供的隔离特征，实现放大器元件之间的信号隔离的显着改进，从而提高双路放大器的性能。

公开(公告)号：US20110163439A1

公开(公告)日：2011-07-07

申请号：US12683961

申请日：2010-01-07

Applicant: Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

Inventor： Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract translation: 一种方法包括提供含硅模头并且在散热器的第一表面上提供具有钯层的散热器。 第一金层位于管芯的第一表面或钯层之一上。 所述含硅芯片与所述散热器接合，其中，所述接合包括将所述含硅芯片与所述散热器接合，使得所述第一金层和所述钯层位于所述含硅模具的所述第一表面和所述第一表面之间 并且加热所述第一金层和所述钯层以在所述含硅芯片的所述第一表面和所述散热器的所述第一表面之间形成管芯附着层，所述管芯附着层包括金界面层，所述金界面层具有 多个金属间化合物沉淀物，多个金属间析出物中的每一个包括钯，金和硅。

公开(公告)号：US20160163623A1

公开(公告)日：2016-06-09

申请号：US15041742

申请日：2016-02-11

Applicant: Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

Inventor： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/49506 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

公开(公告)号：US20160126206A1

公开(公告)日：2016-05-05

申请号：US14530285

申请日：2014-10-31

Applicant: Lakshminarayan Viswanathan ,  Jaynal A. Molla

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3736 ,  H01L23/367 ,  H01L23/3735 ,  H01L24/29 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144

Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

Abstract translation: 半导体器件及其制造方法包括晶片和平面热层，以及直接设置在平面热层的第一平面侧上的至少四（4）微米厚度的厚银层，作为 以及设置在厚银层和模具之间的冶金管芯附着物，冶金管芯附着物直接接触厚银层。