公开(公告)号：US5906042A

公开(公告)日：1999-05-25

申请号：US538886

申请日：1995-10-04

申请人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu ,  John Y. Xie

发明人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu ,  John Y. Xie

IPC分类号： H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/4069 ,  H01L23/5382 ,  H01L23/5384 ,  H05K1/0293 ,  H01L2224/48091 ,  H01L2224/48247 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K3/0023 ,  H05K3/105 ,  H05K3/4644 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A micro filled material includes a binding material and optionally includes a number of particles. The binding material and the particles can be formed of any conductive or nonconductive material. Using such a micro filled via material, an electrical conductor is formed in a substrate for supporting one or more electronic components using the following steps: placing the micro filled via material between two conductive layers at various locations in a substrate at which an electrical conductor is to be formed; and optionally programming the micro filled via material to reduce the resistance of, or to form an electrical conductor.

摘要翻译： 微填充材料包括粘合材料并且任选地包括许多颗粒。 粘结材料和颗粒可由任何导电或非导电材料形成。 使用这种微填充的通孔材料，在用于支撑一个或多个电子部件的基板中形成电导体，所述电导体使用以下步骤：将微填充的通孔材料放置在电导体为基底的基板中的各个位置处的两个导电层之间 要形成 并且可选地编程微填充的通孔材料以降低电导体的电阻或形成电导体。

公开(公告)号：US5872338A

公开(公告)日：1999-02-16

申请号：US631875

申请日：1996-04-10

申请人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

发明人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/44 ,  H05K1/03

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K3/445 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/0733 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4069 ,  Y10T29/49165

摘要： A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes. For example, the support layer can be formed by etching a sheet of conductive material, the compound layers can be formed by placing a conductive paste in via holes in a dielectric layer, and the conductive layers can be formed by lamination followed by etching to form traces.

摘要翻译： 结构包括由诸如铜片的导电材料形成的支撑层。 支撑层具有通过隔离间隙与支撑层的其它部分隔离的多个导电岛。 支撑层夹在两个化合物层之间，每个化合物层由具有多个通孔的电介质层和位于通孔中的导电元件形成。 导电元件形成在预定位置，使得每个化合物层中的导电元件接触支撑层中的导电岛。 该结构还包括在两个相应化合物层上形成的两个导电层，使得第一导电层中的迹线通过两个化合物层中的两个导电元件和支撑层中的岛耦合到第二导电层中的迹线 。 这样的结构可以通过多个过程形成。 例如，可以通过蚀刻导电材料片形成支撑层，可以通过在电介质层中的通孔中放置导电膏来形成化合物层，并且可以通过层压形成导电层，然后进行蚀刻以形成 痕迹

公开(公告)号：US06034427A

公开(公告)日：2000-03-07

申请号：US14693

申请日：1998-01-28

申请人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

发明人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/12

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49883 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48647 ,  H01L2224/49109 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called "programming") to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.

摘要翻译： 集成电路（IC）封装衬底具有基本上形成在电介质层中的孔的中心的电介质层和微填充通孔。 IC封装基板具有至少一个芯片焊盘和一个通过微型填充通孔彼此电耦合的焊球附着焊盘。 微填充通孔由称为“微填充通孔材料”的材料形成，其包括粘合材料，并且任选地包括分散在粘合材料中的许多颗粒（介于0％-90％之间）。 粘合材料可以是任何材料，例如导电或不导电的聚合物。 颗粒可由任何导电材料形成，例如导电聚合物或导电金属（例如铜或金）。 电导体本来可以简单地通过彼此相邻的导电颗粒之间的接触形成。 在可选步骤中，微填充通孔经受编程电流（在称为“编程”的步骤中）以降低原始形成的电导体的电阻，或者通过介电材料的分解原本形成电导体。 IC封装基板可以形成为空腔向上或空腔向下配置。

公开(公告)号：US5987744A

公开(公告)日：1999-11-23

申请号：US888348

申请日：1997-07-01

申请人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

发明人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/44 ,  H01K3/10

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K3/445 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/0733 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4069 ,  Y10T29/49165

摘要： A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes. For example, the support layer can be formed by etching a sheet of conductive material, the compound layers can be formed by placing a conductive paste in via holes in a dielectric layer, and the conductive layers can be formed by lamination followed by etching to form traces.

摘要翻译： 结构包括由诸如铜片的导电材料形成的支撑层。 支撑层具有通过隔离间隙与支撑层的其它部分隔离的多个导电岛。 支撑层夹在两个化合物层之间，每个化合物层由具有多个通孔的电介质层和位于通孔中的导电元件形成。 导电元件形成在预定位置，使得每个化合物层中的导电元件接触支撑层中的导电岛。 该结构还包括在两个相应化合物层上形成的两个导电层，使得第一导电层中的迹线通过两个化合物层中的两个导电元件和支撑层中的岛耦合到第二导电层中的迹线 。 这样的结构可以通过多个过程形成。 例如，可以通过蚀刻导电材料片形成支撑层，可以通过在电介质层中的通孔中放置导电膏来形成化合物层，并且可以通过层压形成导电层，然后进行蚀刻以形成 痕迹

公开(公告)号：US5767575A

公开(公告)日：1998-06-16

申请号：US543982

申请日：1995-10-17

申请人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

发明人： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

IPC分类号： H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/12

CPC分类号： H01L24/73 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/49109 ,  H01L2224/49173 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called "programming") to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.

公开(公告)号：US5726482A

公开(公告)日：1998-03-10

申请号：US319906

申请日：1994-10-07

申请人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  Robert Osann, Jr.

发明人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  Robert Osann, Jr.

IPC分类号： G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/00

CPC分类号： G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2924/0002 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

摘要翻译： 被测器件包括形成为多层结构的一部分的保险丝和/或反熔断矩阵。 保险丝和/或反熔丝的矩阵可以被电编程以将第一电触点中的任何一个连接到第二电触点中的任一个，并且因此允许测试下的卡作为可连接到 信号驱动器和/或接收器以及可以连接到被测器件端子的老化板迹线。 测试卡以下的设备还包括分立电阻器或可选的电阻梯，其允许被测器件的端子耦合到电源或接地端子或电阻的任何组合，包括短路，或另外 作为各种信号驱动器和/或接收器中的任何一个的替代。

公开(公告)号：US5906043A

公开(公告)日：1999-05-25

申请号：US884823

申请日：1997-06-30

申请人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

发明人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

IPC分类号： H05K1/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/4069 ,  H05K1/0293 ,  H05K3/0023 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10689 ,  H05K2203/105 ,  H05K2203/1461 ,  H05K2203/1536 ,  H05K2203/173 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4652 ,  Y10T29/49016 ,  Y10T29/49165

摘要： In one embodiment, the steps for forming an electrical conductor between conductive layers of a printed circuit board include the following steps: (1) applying a first dielectric material on a first conductive layer; (2) forming a number of via holes at each of the predetermined locations in the first dielectric material at which an electrical conductor is to be formed; (3) selectively applying a second dielectric material to at least fill each of the via holes, to form a composite dielectric layer; (4) applying a second conductive layer on the composite dielectric layer; (5) etching the first conductive layer to form a first electrode; (6) etching the second conductive layer to form a second electrode; and (7) applying a programming voltage across the second dielectric material in each of the via holes to form an electrical conductor in each of the via holes, each electrical conductor connecting an electrode in the first conductive layer to an electrode in the second conductive layer.

摘要翻译： 在一个实施例中，用于在印刷电路板的导电层之间形成电导体的步骤包括以下步骤：（1）在第一导电层上施加第一介电材料; （2）在要形成电导体的第一介电材料中的每个预定位置处形成多个通孔; （3）选择性地施加第二电介质材料以至少填充每个通孔，以形成复合电介质层; （4）在复合介电层上施加第二导电层; （5）蚀刻第一导电层以形成第一电极; （6）蚀刻所述第二导电层以形成第二电极; 和（7）在每个通孔中的第二电介质材料上施加编程电压以在每个通孔中形成电导体，每个电导体将第一导电层中的电极连接到第二导电层中的电极 。

公开(公告)号：US5962815A

公开(公告)日：1999-10-05

申请号：US374941

申请日：1995-01-18

申请人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

发明人： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

IPC分类号： H05K1/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H01R9/09

CPC分类号： H05K3/4069 ,  H05K1/0293 ,  H05K3/0023 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10689 ,  H05K2203/105 ,  H05K2203/1461 ,  H05K2203/1536 ,  H05K2203/173 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4652 ,  Y10T29/49016 ,  Y10T29/49165

摘要： A multilayered structure, such as a printed circuit board, includes a first conductive layer and a second conductive layer that are separated from each other by a dielectric layer. The dielectric layer is formed of a first material, such as a photoimagible polyimide and epoxy resin. The dielectric layer has a number of via holes that extend from the first conductive layer to the second conductive layer. The via holes are filled with a second material having a breakdown voltage less than a breakdown voltage of the first material included in the dielectric layer to form an antifuse. The second material in the via holes can be, for example, a conductive epoxy resin or a polymer loaded with conductive particles (also referred to as "conductive paste").

摘要翻译： 诸如印刷电路板的多层结构包括通过电介质层彼此分离的第一导电层和第二导电层。 电介质层由第一材料形成，例如光可塑性聚酰亚胺和环氧树脂。 电介质层具有从第一导电层延伸到第二导电层的多个通孔。 通孔填充有具有小于包含在电介质层中的第一材料的击穿电压的击穿电压以形成反熔丝的第二材料。 通孔中的第二材料可以是例如导电环氧树脂或负载有导电颗粒的聚合物（也称为“导电糊”）。

公开(公告)号：US5537108A

公开(公告)日：1996-07-16

申请号：US319851

申请日：1994-10-07

申请人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

发明人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

IPC分类号： G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H04Q1/18

CPC分类号： G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.

摘要翻译： 根据本发明的编程方法将熔丝矩阵的迹线分成组，其中每组包含连接到保持完整的熔丝的迹线。 组中的所有迹线都连接到第一电压，使得组中迹线之间的熔丝经受最小电流。 在一个实施例中，不在连接到第一电压的组中的所有迹线被连接到第二电压，使得编程电流通过待编程的熔丝。 在替代实施例中，第二组中的迹线连接到第二电压，并且所有剩余的迹线彼此短接。

公开(公告)号：US5572409A

公开(公告)日：1996-11-05

申请号：US319860

申请日：1994-10-07

申请人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

发明人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

IPC分类号： G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H05K7/06 ,  H01R9/09

CPC分类号： G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.

摘要翻译： 在一个实施例中，公开了两种类型的可编程元件，熔丝和反熔丝，用于形成电可编程插座适配器。 插座适配器可用于将具有第一配置的端子的电子部件与印刷电路板中的电触点相互连接。