公开(公告)号：US09455240B2

公开(公告)日：2016-09-27

申请号：US14138164

申请日：2013-12-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/743 ,  H01L24/97 ,  H01L2224/10175 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract translation: 提高了半导体器件的可靠性。 形成在布线基板中的芯片安装面上的多个端子中的每一个在平面图中具有窄宽度部分布置在相邻的宽幅部分之间的形状。 此外，形成在安装在布线基板上的半导体芯片上的多个突起电极中的每一个的前端面的中心布置在与平面图中的窄宽度部分重叠的位置，并且多个端子和 多个突出电极经由焊料构件彼此电连接。

公开(公告)号：US09349678B2

公开(公告)日：2016-05-24

申请号：US14750009

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Ono ,  Nobuhiro Kinoshita ,  Tsuyoshi Kida ,  Jumpei Konno ,  Kenji Sakata ,  Kentaro Mori ,  Shinji Baba

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2224/45147

Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.

Abstract translation: 提高了半导体器件的可靠性。 在覆盖有保护绝缘膜的焊盘的探针区域上形成探针标记。 并且，柱状电极具有形成在开口区域上的第一部分和从开口区域的上部在探针区域上延伸的第二部分。 此时，开口区域的中心位置从与接合手指相对的柱状电极的中心位置偏移。

公开(公告)号：US20140312498A1

公开(公告)日：2014-10-23

申请号：US14229981

申请日：2014-03-30

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Jumpei Konno

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48111 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/0052 ,  H05K3/326 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0665

Abstract: To provide a semiconductor device having improved reliability.In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.

Abstract translation: 提供具有提高的可靠性的半导体器件。 在BGA的布线基板中，绝缘层上具有多个接合引线。 绝缘层由具有玻璃布的预浸料和不具有玻璃布的树脂层构成。 预浸料在其上具有树脂层。 接合引线直接配置在软树脂层上，由此软树脂层支撑。 当在倒装芯片接合期间对每个接合引线施加负载时，树脂层下沉，由此可以放松施加到半导体芯片的应力。

公开(公告)号：US09818678B2

公开(公告)日：2017-11-14

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

公开(公告)号：US20140183759A1

公开(公告)日：2014-07-03

申请号：US14138164

申请日：2013-12-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L23/00 ,  H01L23/49

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/743 ,  H01L24/97 ,  H01L2224/10175 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract translation: 提高了半导体器件的可靠性。 形成在布线基板中的芯片安装面上的多个端子中的每一个在平面图中具有窄宽度部分布置在相邻的宽幅部分之间的形状。 此外，形成在安装在布线基板上的半导体芯片上的多个突起电极中的每一个的前端面的中心布置在与平面图中的窄宽度部分重叠的位置，并且多个端子和 多个突出电极经由焊料构件彼此电连接。