公开(公告)号：US08115300B2

公开(公告)日：2012-02-14

申请号：US11763053

申请日：2007-06-14

申请人： Shigetsugu Muramatsu ,  Tsuyoshi Kobayashi ,  Takashi Kurihara

发明人： Shigetsugu Muramatsu ,  Tsuyoshi Kobayashi ,  Takashi Kurihara

IPC分类号： H01L23/12

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/48227 ,  H05K1/111 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y02P70/611

摘要： In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with an insulating layer. Surfaces of connection parts of the wiring patterns formed on the tops of the protrusions are formed with the surfaces of the connection parts exposed to a surface of the insulating layer on a level with the surface of the insulating layer or in a position lower than the surface of the insulating layer. The connection parts are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element is mounted by making electrical connection to the connection parts by flip chip bonding.

摘要翻译： 在半导体装置中，将半导体元件安装在布线基板上。 布线图案和突起形成在基板的表面上，布线图案在突起的顶部延伸。 其上形成有布线图案的基板的表面被绝缘层覆盖。 形成在突起的顶部上的布线图形的连接部分的表面形成有连接部分的表面暴露于绝缘层的表面与绝缘层的表面或低于表面的位置 的绝缘层。 连接部分形成为与半导体元件的连接电极对准形成的用于连接的焊盘。 半导体元件通过倒装芯片接合与连接部分进行电连接来安装。

公开(公告)号：US20070290306A1

公开(公告)日：2007-12-20

申请号：US11763053

申请日：2007-06-14

申请人： Shigetsugu Muramatsu ,  Tsuyoshi Kobayashi ,  Takashi Kurihara

发明人： Shigetsugu Muramatsu ,  Tsuyoshi Kobayashi ,  Takashi Kurihara

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/48227 ,  H05K1/111 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y02P70/611

摘要： In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with an insulating layer. Surfaces of connection parts of the wiring patterns formed on the tops of the protrusions are formed with the surfaces of the connection parts exposed to a surface of the insulating layer on a level with the surface of the insulating layer or in a position lower than the surface of the insulating layer. The connection parts are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element is mounted by making electrical connection to the connection parts by flip chip bonding.

摘要翻译： 在半导体装置中，将半导体元件安装在布线基板上。 布线图案和突起形成在基板的表面上，布线图案在突起的顶部延伸。 其上形成有布线图案的基板的表面被绝缘层覆盖。 形成在突起的顶部上的布线图形的连接部分的表面形成有连接部分的表面暴露于绝缘层的表面与绝缘层的表面或低于表面的位置 的绝缘层。 连接部分形成为与半导体元件的连接电极对准形成的用于连接的焊盘。 半导体元件通过倒装芯片接合与连接部分进行电连接来安装。

公开(公告)号：US06455786B1

公开(公告)日：2002-09-24

申请号：US09539117

申请日：2000-03-30

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

IPC分类号： H05K116

CPC分类号： H01L23/3114 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.

摘要翻译： 半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。 提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由 外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

公开(公告)号：US06444494B1

公开(公告)日：2002-09-03

申请号：US09412976

申请日：1999-10-06

申请人： Shigetsugu Muramatsu ,  Takashi Kurihara

发明人： Shigetsugu Muramatsu ,  Takashi Kurihara

IPC分类号： H01L2148

CPC分类号： H01L24/86 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Semiconductor devices are manufactured, using film substrates, as follows. Individual film substrates are separated from a film substrate tape having a plurality of film substrates continuously and integrally connected to each other, each the film substrate comprising a base film having first and second surfaces, a circuit pattern being formed on the first surface and a mounting section being formed on the second surface. The base film has an opening to which electrode terminals of a semiconductor element are exposed when the semiconductor element is mounted. The individual film substrates are adhered to respective reinforcement members of a reinforcement frame, which has a plurality of the reinforcement members continuously and integrally connected to each other. Each reinforcement member has an accommodation hole for accommodating the semiconductor element, so that the semiconductor element mount section is exposed in the accommodation hole. A semiconductor element is mounted on the film substrate by adhering an electrode terminal-forming surface of the semiconductor element to said mounting section so that electrode terminals of the semiconductor element are exposed in the accommodation hole. The electrode terminals exposed in the opening are electrically connected to the circuit patterns. The opening is sealed with resin and then the individual reinforcement members are separated from the reinforcement frame.

摘要翻译： 使用膜基板制造半导体器件，如下。 各个薄膜基板与具有多个薄膜基片的薄膜基片分离，所述薄膜基片彼此连续且一体地连接，每个薄膜基片包括具有第一表面和第二表面的基底膜，在第一表面上形成电路图案， 形成在第二表面上。 当安装半导体元件时，基膜具有露出半导体元件的电极端子的开口。 各个胶片基材粘附到加强框架的相应的加强构件上，该加强框架具有连续且一体地连接的多个加强构件。 每个加强构件具有用于容纳半导体元件的容纳孔，使得半导体元件安装部暴露在容纳孔中。 半导体元件通过将半导体元件的电极端子形成表面粘附到所述安装部分而安装在膜基底上，使得半导体元件的电极端子露出在容纳孔中。 暴露在开口中的电极端子电连接到电路图案。 开口用树脂密封，然后各个加强构件与加强框架分离。

公开(公告)号：US20070200211A1

公开(公告)日：2007-08-30

申请号：US11705402

申请日：2007-02-13

申请人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu

发明人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu

IPC分类号： H01L23/495

CPC分类号： H01L23/5226 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09645 ,  H05K2201/09827 ,  H01L2924/00

摘要： In the case in which an electrical connection between upper and lower layers is to be carried out through a via opening portion 16 provided on an insulating layer 14 of a wiring substrate constituting a multilayer wiring substrate, the electrical connection between the upper and lower layers is performed through a conductive material 30 while exposing a part of wall surfaces of the via opening portion 16 of the insulating layer without covering all of the wall surfaces of the via opening portion 16 with the conductive material 30.

摘要翻译： 在通过设置在构成多层布线基板的布线基板的绝缘层14上的通孔开口部16进行上下层之间的电连接的情况下，上层和下层之间的电连接是 同时通过绝缘层的通孔开口部分16的一部分壁表面暴露，而不用导电材料30覆盖通孔开口部分16的所有壁表面。

公开(公告)号：US07180182B2

公开(公告)日：2007-02-20

申请号：US10492556

申请日：2002-10-11

申请人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu ,  Takuya Kazama

发明人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu ,  Takuya Kazama

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L23/525 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor component having electrode terminals 14 formed in rectangular planar shapes arranged in parallel on an electrode forming surface of a semiconductor chip and formed with rerouting patterns 16 electrically connected with the electrode terminals 14 through vias on the surface of an electrical insulating layer covering the electrode forming surface, characterized in that the planar arrangement of the via pads 20 formed on the surface of the electrical insulating layer is made an arrangement alternately offset to one side and the other side of the longitudinal direction of the electrode terminals 14 and in that rerouting patterns 16 are provided connected to the via pads 20. The present invention enables easy formation of rerouting patterns even when the electrode terminals are arranged at fine intervals.

摘要翻译： 一种半导体元件，其具有形成为矩形平面形状的矩形平面形状的半导体元件，该半导体元件平行地形成在半导体芯片的电极形成表面上，并且形成有重新布线图案16，其通过在覆盖电极的电绝缘层的表面上的电极端子14电连接 形成表面的特征在于，形成在电绝缘层的表面上的通孔焊盘20的平面布置被制成交替地偏移到电极端子14的纵向方向的一侧和另一侧，并且在该重新布线图案 16被连接到通孔焊盘20。 本发明即使当电极端子以精细的间隔布置时，也能够容易地形成重新布线图案。

公开(公告)号：US20110316170A1

公开(公告)日：2011-12-29

申请号：US13166083

申请日：2011-06-22

申请人： Shigetsugu Muramatsu ,  Satoshi Sunohara

发明人： Shigetsugu Muramatsu ,  Satoshi Sunohara

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/15151 ,  H01L2924/00012 ,  H01L2924/00

摘要： A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.

摘要翻译： 布线基板包括在包括焊盘的最上层中的布线图案。 阻焊层覆盖布线图案。 凹陷使得阻焊层的部分布线图案露出以形成焊盘。 阻焊层包括形成在与凹部对应的区域中的部分，从凹部向外形成的部分和从凹部向内形成的部分。 阻焊层的与凹部对应的部分的上表面高于焊盘的上表面，但低于阻焊层的其它部分的上表面。

公开(公告)号：US20110253422A1

公开(公告)日：2011-10-20

申请号：US13150691

申请日：2011-06-01

申请人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

发明人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC分类号： H05K1/02

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

摘要翻译： 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US06628527B2

公开(公告)日：2003-09-30

申请号：US09741481

申请日：2000-12-20

申请人： Shigetsugu Muramatsu ,  Takuya Kazama

发明人： Shigetsugu Muramatsu ,  Takuya Kazama

IPC分类号： H05K702

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15331 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49135 ,  H01L2224/81 ,  H01L2224/05599

摘要： A unit interconnection substrate for mounting leadless type electronic parts on a mount substrate by superposing them on each other in two or more stages, comprising an insulating surface on the top surface of which an interconnection circuit with conductor pads and connection terminals is formed, depressions for holding electronic parts formed in a bottom surface of the insulating substrate, connection terminals provided on the bottom surface of the insulating substrate on the periphery of the depression, and connection terminals electrically connected to the connection terminals of the top surface of the insulating substrate via conductor via holes provided in the insulating substrate. Electronic parts are electrically connected to the conductor pads on the top surface of the insulating substrate, thereby to make it possible to mount the electronic parts on the insulating substrate. Together with this, holding of the electronic parts mounted on the mount substrate in the depressions of the bottom surface of the insulating substrate is made possible.

摘要翻译： 一种单元互连基板，用于通过将安装基板上的无引线型电子部件彼此叠置在两个或更多个阶段中来安装无引线型电子部件，所述两个或多个阶段包括在其顶表面上形成有与导体焊盘和连接端子的互连电路的绝缘表面， 保持形成在所述绝缘基板的底面的电子部件，设置在所述凹部的周围的所述绝缘基板的底面上的连接端子，以及通过导体电连接到所述绝缘基板的上表面的连接端子的连接端子 通孔设置在绝缘基板中。 电子部件电连接到绝缘基板的顶表面上的导体焊盘，从而可以将电子部件安装在绝缘基板上。 与此同时，能够将安装在安装基板上的电子部件保持在绝缘基板的底面的凹部中。

公开(公告)号：US06404214B1

公开(公告)日：2002-06-11

申请号：US09468060

申请日：1999-12-20

申请人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

发明人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

IPC分类号： G01R3102

CPC分类号： H05K1/112 ,  G01R31/2886 ,  H01L2224/16237 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/325 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10734

摘要： A substrate for inspecting an electronic device used for an electrical test of the electronic device having bump-shaped connection terminals, comprises: opening sections, the diameter of each opening being determined so that a connection terminal can be inserted into and drawn out from the opening, are formed penetrating the insulating substrate in a region on one side of an insulating substrate on which the electronic device is mounted, corresponding to an arrangement of the connection terminals; and wiring patterns, each of which is composed of a pad section being exposed onto a bottom face of the opening so that the pad can come into contact with the connection terminal so as to accomplish electrical continuity, a connecting pad section formed in a region outside of the region in which the pad section is formed, which comes into contact with a contact terminal of an inspection device so as to accomplish electrical continuity, and a wiring section for electrically connecting the pad section with the connecting pad section, are formed on the other side of the insulating substrate.

摘要翻译： 一种用于检查用于具有凸起形连接端子的电子设备的电气测试的电子设备的基板，包括：开口部分，每个开口的直径被确定为使得连接端子能够从开口插入和拉出 对应于连接端子的布置，在安装有电子设备的绝缘基板的一侧的区域中穿过绝缘基板; 以及布线图案，每个布线图案由暴露于开口的底面的焊盘部分组成，使得焊盘能够与连接端子接触以实现电连续性;连接焊盘部分形成在外部区域 形成有与检查装置的接触端子接触以实现电连续性的形成有焊盘部的区域，以及用于将焊盘部与连接焊盘部电连接的布线部，形成在 绝缘基板的另一侧。