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    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
    1.
    发明申请
    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer 审中-公开
    用于通过基板晶片制造具有完全金属化通孔的封装接口基板晶片的技术

    公开(公告)号：US20090302454A1

    公开(公告)日：2009-12-10

    申请号：US12462980

    申请日：2009-08-11

    申请人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    发明人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

    摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

    摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
    2.
    发明授权
    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer 有权
    用于通过基板晶片制造具有完全金属化通孔的封装接口基板晶片的技术

    公开(公告)号：US07880305B2

    公开(公告)日：2011-02-01

    申请号：US10290049

    申请日：2002-11-07

    申请人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    发明人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

    摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

    摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

    Method for forming Co-W-P-Au films
    7.
    发明授权
    Method for forming Co-W-P-Au films 失效
    Co-W-P-Au薄膜的制备方法

    公开(公告)号：US06323128B1

    公开(公告)日：2001-11-27

    申请号：US09320499

    申请日：1999-05-26

    申请人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

    发明人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

    IPC分类号： H01L21441

    CPC分类号： H01L21/76846 ,  C23C18/1651 ,  C23C18/1841 ,  C23C18/44 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76874 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

    摘要翻译： 公开了一种用于在半导体结构中的铜互连上用作扩散阻挡层的Co-W-P-Au的四元合金膜的形成方法和包含这种膜的器件。 在该方法中，首先通过两个单独的预处理步骤对具有铜导电区域的基板进行预处理。 在第一步骤中，将衬底浸入H 2 SO 4冲洗溶液中，接着在含有钯离子的溶液中浸渍一段足以使离子沉积在铜导电区域表面上的时间。 然后将基底浸入含有至少15g / l柠檬酸钠或EDTA的溶液中，以从铜导电区域的表面除去过量的钯离子。 在通过蒸馏水在第一冲洗步骤中冲洗预处理的基材之后，在包含钴离子，钨酸根离子，柠檬酸根离子的第一电镀液中，在铜导电区域的表面上化学镀Co-WP膜 和还原剂。 在用Co-W-P膜涂布的基材在第二次漂洗步骤中用蒸馏水冲洗后，将基板浸渍在Co-W-P膜顶部沉积Au层的第二无电镀液中。 本发明的新型四元合金膜可以用作铜互连和硅衬底或SiO 2电介质层之间的有效扩散阻挡层。