公开(公告)号：EP1137333A1

公开(公告)日：2001-09-26

申请号：EP99943231.3

申请日：1999-09-08

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, N., Ogaki-kita-kojou ,  EN, Honjin, Ogaki-kita-kojou

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 µ m. The reason is as follows. If the diameter of the mesh hole is less than 75 µ m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 µ m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 µ m. The reason is as follows. If the distance is less than 100 µ m, the solid layer cannot function. If the distance exceeds 2000 µ m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract translation: 上固体层35和上固体层59的网孔35a和59a形成为彼此叠置，使得层间树脂绝缘层50的绝缘性能不降低。 这里，每个网孔的直径优选为75〜300μm。 原因如下。 如果网孔的直径小于75μm，则难以将上，下网孔叠置在一起。 如果直径超过300μm，则层间树脂绝缘层的绝缘性变差。 此外，网眼之间的距离优选为100〜2000μm。 原因如下。 如果距离小于100微米，则固体层不能起作用。 如果距离超过2000μm，则发生层间树脂绝缘膜的绝缘性的劣化。

公开(公告)号：EP1130950A2

公开(公告)日：2001-09-05

申请号：EP01104820.4

申请日：2001-02-27

Applicant: Kyocera Corporation

Inventor： Takeshita Yoshihiro c/o KYOCERA CORPORATION ,  Terao Shinya c/o Kyocera corporation ,  Takenouchi Satoruc/o Kyocera corporation ,  KajiMasaki c/o Kyocera corporation ,  Koga, Ryuji

IPC: H05K1/02 ,  H05K1/16 ,  H01L23/498

CPC classification number: H05K1/0234 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A wiring board (1) of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer (5) and a ground layer (6) over a broad range of frequencies with a simple arrangement. The wiring board (1) has an on-board surface (3) on the surface of a dielectric substrate (2), on which a semiconductor device (4) or the like is mounted, and a power source layer (5) and a ground layer (6), which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate (2) or within the same. The periphery of at least one of low resistance areas (5a, 6a) of the power source layer (5) and ground layer (6), respectively is provided with a corresponding high resistance area (5b or 6b) having a higher sheet resistance than that of the respective low resistance areas (5a, 5b).

公开(公告)号：EP1112672A1

公开(公告)日：2001-07-04

申请号：EP99938904.2

申请日：1999-07-30

Applicant: Kulicke & Soffa Holdings, Inc.

Inventor： STRANDBERG, Jan, I. ,  CHAZAN, David, J. ,  SKINNER, Michael, P.

IPC: H05K1/03

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: Low-impedance high-density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

公开(公告)号：EP0954020A2

公开(公告)日：1999-11-03

申请号：EP99107191.1

申请日：1999-04-13

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Saitoh, Tohru

IPC: H01L21/60 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/07802 ,  H05K1/0271 ,  H05K2201/093 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Lands (1) for bonding a flip chip (3) are provided in a surface layer of a printed board (5). A dummy pattern or ground pattern (2) for preventing waving is provided on a layer next to the surface layer. The interlaminar thickness is made uniform by the dummy pattern or ground pattern (2). Since the flip chip bonding lands are arranged substantially in a plane, the flip chip lands are supported by the dummy or ground pattern to prevent waving from occurring so that high bonding quality can be obtained. In contrast to an arrangement in which a dummy pattern is not provided partially in a portion where bonding becomes unstable, a dummy pattern or a ground pattern is provided in an area corresponding to the outer shape of a flip chip to thereby support all the bonding lands of the flip chip. The flip chip bonding lands are kept in a uniform plane to suppress waving of the printed board so that bonding can be effected surely.

公开(公告)号：EP0836369A3

公开(公告)日：1999-10-06

申请号：EP97202818.7

申请日：1997-09-15

Applicant: Philips Patentverwaltung GmbH ,  Philips Electronics N.V.

Inventor： Schiltmans, Ronald ,  Avramis, Evangelos

IPC: H05K1/11

CPC classification number: H05K1/0239 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0243 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10727 ,  H05K2201/10969 ,  H01L2924/00

Abstract: Die Erfindung bezieht sich auf eine Leiterplatte mit einer auf ihrer Unterseite angeordneten Metallschicht (15) und mit auf ihrer Oberseite angeordneten HF-Bausteinen (11, 12), die eingangsseitig und/oder ausgangsseitig über Mikrostreifen-Zuleitungen (13, 14) mit HF-Quellen, HF-Senken oder anderen HF-Bausteinen und über eine gesonderte Zuleitung (20) mit einer Gleichstromquelle (21) verbindbar sind. Um eine stromsparende Reihenschaltung von mindestens zwei HF-Bauteilen (11, 12) zu ermöglichen, wird gemäß der Erfindung vorgeschlagen,
daß die Metallschicht (15) im Anschlußbereich mindestens eines HF-Bausteines (11) durch einen Spalt (16) galvanisch von der benachbarten Metallschicht (15) getrennt ist und daß die so gebildete metallische Insel (17) im Bereich unterhalb der dem HF-Baustein (11) zugeordneten Mikrostreifen-Zuleitung (13) HF-mäßig mit der benachbarten Metallschicht (15) gekoppelt ist.

Abstract translation: 电路板具有施加到其下侧的金属层，其中安装在其顶表面上的用于微波电路的HF部件（11,12）经由微带线（13,14）耦合到其它HF部件，并经由电流耦合到DC源 线（20）。 至少一个HF组分（11）下面的金属层的区域通过间隙（16）与金属层的其余部分分离，以在微带线（13）下方形成岛（17）。

公开(公告)号：EP0575892B1

公开(公告)日：1999-08-11

申请号：EP93109693.7

申请日：1993-06-17

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Oshima, Seiichi, c/o Mitsubishi Denki K.K: ,  Tametani,Fumitaka c/c Mitsubishi Denki K.K. ,  Yamagata,Jun c/o Fukuryo Semiconductor Eng.Corp. ,  Takanashi,Ken c/o Mitsubishi Denki K.K.

IPC: H01L25/16 ,  H01L23/64 ,  H05K9/00

CPC classification number: H01L25/162 ,  H01L23/5383 ,  H01L23/642 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0262 ,  H05K1/144 ,  H05K9/0039 ,  H05K2201/093 ,  H05K2201/10015 ,  H05K2201/10689 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

公开(公告)号：EP0817548A1

公开(公告)日：1998-01-07

申请号：EP96942586.7

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： MORI, Yoji ,  KAWAMURA, Yoichiro

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.

Abstract translation: 印刷电路板，其中存在于作为光电二极管的焊盘周围的开口布置成使其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且设置从每个开口溢出的树脂量或当树脂在每个开口中填充或均匀时。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现其中安全连接不会导致断开的可靠的印刷线路板 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

公开(公告)号：EP0767600A1

公开(公告)日：1997-04-09

申请号：EP96402079.6

申请日：1996-09-30

Applicant: MATRA COMMUNICATION

Inventor： Chapon, Thierry

IPC: H05K3/34

CPC classification number: H05K1/113 ,  H05K1/0201 ,  H05K1/0243 ,  H05K3/0094 ,  H05K3/3442 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/1006 ,  H05K2201/10969

Abstract: Le dispositif comprend un substrat multicouche et au moins un composant (14) monté en surface dudit substrat. Le substrat comporte un plan de masse interne et un plan de masse externe (26) compris dans la surface sur laquelle est monté le composant, avec des trous métallisés de rappel de masse (38) reliant les plans de masse interne et externe. Le composant (14) a au moins une portion soudée sur une plage métallisée respective (32) appartenant au plan de masse externe (26). Cette plage métallisée (32) a un périmètre partiellement non métallisé (34) formant frein thermique. Au moins un des trous de rappel de masse (38) est situé à l'intérieur dudit périmètre non métallisé (34). Application à des filtres passe-bande, des mélangeurs ou des amplificateurs de puissance.

Abstract translation: 部件（14）至少部分地焊接到属于外部接地平面（26）的金属化突片（32），并且具有形成阻燃剂的部分未金属化的周边（34），其中至少一个 金属化接地回路孔（38）位于。 其上安装有部件的基板表面具有与外部接地平面（26）绝缘的共面金属化线，以便连接部件的访问信号。 非金属化区域的宽度为约1mm，金属化连接（36）穿过约0.5mm宽度的周边，得到10-20mm 2的区域片。

公开(公告)号：EP0766503A2

公开(公告)日：1997-04-02

申请号：EP96115548.8

申请日：1996-09-27

Applicant: CANON KABUSHIKI KAISHA

Inventor： Ohtaki, Toru, c/o Canon K.K. ,  Ichida, Yasuteru, c/o Canon K.K. ,  Takeuchi, Yasushi, c/o Canon K.K.

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H01L23/48 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3421 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.

公开(公告)号：EP0663142B1

公开(公告)日：1996-08-21

申请号：EP93924900.9

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： GEBARA, Ghassan, R.

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K9/0039 ,  H05K2201/093

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.