公开(公告)号：EP1968364A1

公开(公告)日：2008-09-10

申请号：EP08150950.7

申请日：2008-02-01

Applicant: NITTO DENKO CORPORATION

Inventor： Kamei, Katsutoshi ,  Yokai, Takahiko ,  Thaveeprungsriporn, Visit

IPC: H05K3/24 ,  H05K1/05

CPC classification number: H05K3/243 ,  H05K1/056 ,  H05K3/244 ,  H05K3/28 ,  H05K3/384 ,  H05K2201/09472 ,  H05K2203/0361 ,  H05K2203/0577

Abstract: A wired circuit board (1) includes an insulating base layer (3), a conductive pattern (4) formed on the insulating base layer and including a wire (7) and a terminal portion (8), an insulating cover layer (6) formed on the insulating base layer and having an opening portion (11) to expose the terminal portion, and a metal thin film (5) including a protecting portion (9) interposed between the wire and the insulating cover layer, and an exposed portion (10) formed continuously from the protecting portion on a peripheral end portion (16) of the terminal portion exposed from the opening portion.

Abstract translation: 本发明提供一种布线电路基板（1），该布线电路基板（1）具备：基底绝缘层（3）;在基底绝缘层上形成的导线图案（4），该导线图案包含导线（7）和端子部（8） ，其形成在基底绝缘层上并具有用于暴露端子部分的开口部分（11）;以及金属薄膜（5），其包括插入在导线和绝缘覆盖层之间的保护部分（9）以及暴露部分 10）从所述开口部露出的所述端子部的周端部（16）的所述保护部连续形成。

公开(公告)号：EP1961041A2

公开(公告)日：2008-08-27

申请号：EP06835649.2

申请日：2006-12-04

Applicant: Nederlandse Organisatie voor Toegepast-Natuurwetenschappelijk Onderzoek TNO

Inventor： SMULDERS, Edwin, Johannes, Theodorus ,  PUIK, Erik, Christian, Nicolaas

IPC: H01L21/60

CPC classification number: H05K3/321 ,  B81C99/002 ,  B81C2203/032 ,  H01L21/6835 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2924/15312 ,  H05K3/28 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2203/0178 ,  H05K2203/1105 ,  H05K2203/1121 ,  H05K2203/1446

Abstract: Method and system for depositing a frozen adhesive particle at a predetermined spot on a target body, comprising launching means (13) which are arranged to launch the particle (2) in its frozen form towards the target body (3, 4) via a movement path (14) through a gap (15) between the launching means and the target body. The medium in the gap may have a temperature above the adhesive particle's melting temperature. The launching means may be arranged to launch the particle at a high speed. The launching means and the target body may have a geometry causing that the movement path is substantially vertical or substantially horizontal.

公开(公告)号：EP1909322A1

公开(公告)日：2008-04-09

申请号：EP06766961.4

申请日：2006-06-20

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： KIMURA, Masahiro c/o MURATA MANUFACT. CO., LTD., ,  SAITO, Yoshifumi c/o MURATA MANUFACT. CO., LTD.,

IPC: H01L23/12 ,  H01L25/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/183 ,  H05K3/245 ,  H05K3/28 ,  H05K3/284 ,  H05K3/3421 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/308 ,  Y02P70/611 ,  Y10T29/49002 ,  H01L2924/00

Abstract: When a multilayer electronic component having a ceramic substrate and a resin layer is mounted on a mounting substrate, the thickness of solder used in the above mounting is made not to interfere with reduction in size and height of an electronic device including the above multilayer electronic component. Recess portions (8, 9) are formed at an outside-facing major surface (7) side of a resin layer (5). In the resin layer (5), columnar conductors (10, 11) are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer (5). End portions (14, 15) of the columnar conductors (10, 11) are located inside the recess portions (8, 9) further from opening faces thereof and have end surfaces (16, 17) exposed in the recess portions (8, 9). When a multilayer electronic component (1) is mounted on a mounting substrate (26), solder is provided on the end surfaces (16, 17) of the columnar conductors (10, 11) in the recess portions (8, 9).

Abstract translation: 当被安装在安装基板具有陶瓷基板和树脂层的层叠型电子元器件，在上述安装用焊料的厚度为不与包含上述层叠型电子元器件小型化和高度的电子装置的干扰 ， 凹部（8,9）是在形成为树脂层（5）的面向外主表面（7）侧。 在树脂层（5），柱状导体（10，11）被布置成确实轴线方向记载于上述树脂层的厚度方向对准的（5）。 柱状导体的端部（14，15）（10,11）位于所述凹部内（8,9）进一步从开口部的面和具有所述凹部（8,9露出的端表面（16，17） ）。 当多层电子元件（1）被安装在安装基板（26）上，焊料被设置在凹部的柱状导体（10，11）的端表面（16，17）上（8,9）。

公开(公告)号：EP1895589A2

公开(公告)日：2008-03-05

申请号：EP07122506.4

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： The designation of the inventor has not yet been filed

IPC: H01L23/50 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board composed as a multi-layer wiring board, comprising a plurality of conductor circuits (158U,158D) formed in an outermost layer, an insulating layer (150) for supporting a plurality of said conductor circuits formed in said outermost layer and a plurality of inner layer conductor circuits formed under said insulating layer, wherein a plurality of said inner layer conductor circuits are a power supply layer (58U) and/or a ground layer (58D), a soldering bump (76U,76D) is formed, through said insulting layer, on each via-hole (160U,160D) connected to an inner layer conductor circuit.

Abstract translation: 本发明涉及一种作为多层布线板构成的封装板，包括形成在最外层的多个导体电路（158U，158D），用于支撑形成在所述第一层中的多个所述导体电路的绝缘层（150） 最外层和形成在所述绝缘层下面的多个内层导体电路，其中多个所述内层导体电路是电源层（58U）和/或接地层（58D），焊接凸块（76U，76D ）通过所述绝缘层形成在连接到内层导体电路的每个通孔（160U，160D）上。

公开(公告)号：EP1143379B1

公开(公告)日：2008-02-06

申请号：EP01400857.7

申请日：2001-04-03

Applicant: SAGEM Sécurité

Inventor： Darnault, Patrick

IPC: G06K19/077

CPC classification number: G06K19/07769 ,  G06K19/07743 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2924/01057 ,  H05K3/0047 ,  H05K3/321 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2203/0207 ,  H01L2924/00014 ,  H01L2924/00

公开(公告)号：EP1487060A3

公开(公告)日：2007-11-07

申请号：EP04394034.5

申请日：2004-06-11

Applicant: Nortel Networks Limited

Inventor： Kwong, Herman ,  Difilippo, Luigi ,  Wyrzykowska, Aneta

IPC: H05K3/36 ,  H01R12/06

CPC classification number: H01R12/523 ,  H01R12/57 ,  H01R13/642 ,  H01R13/665 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/365 ,  H05K3/368 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/10659 ,  H05K2203/061 ,  Y10T409/300112 ,  Y10T409/300616

Abstract: A circuit device for interconnecting first and second multilayer circuit boards is described herein. The first multilayer circuit board may include a first plurality of electrically conductive vias of varying depths and the second multilayer circuit board may include a second plurality of electrically conductive vias. The circuit device comprises a first plurality of pins located on a first side of the circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin having a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board. The circuit device further comprises a second plurality of pins located on a second side of the circuit device corresponding to the second plurality of electrically conductive vias of the second multilayer circuit board.

公开(公告)号：EP1523229B1

公开(公告)日：2007-10-24

申请号：EP04025133.2

申请日：1999-06-30

Applicant: FormFactor, Inc.

Inventor： Pedersen, David V. ,  Eldridge, Benjamin N. ,  Khandros, Igor Y.

IPC: H05K3/32 ,  G01R1/04

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements (516), such as spring contact elements, extending from electronic components (518), such as semiconductor devices. Socket substrates (504) are provided with capture pads (506) for receiving ends of elongate interconnection elements (516) extending from electronic components (518). Various capture pad configurations are disclosed. A securing device such as a housing (520) positions the electronic component securely to the socket substrate (504). Connections to external devices are provided via conductive traces (510) adjacent the surface of the socket substrate. The socket substrate (504) may be supported by a support substrate (502). In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

公开(公告)号：EP1827065A3

公开(公告)日：2007-10-10

申请号：EP07075318.1

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method of producing a printed wiring board (3) comprising a mounting recess portion (1) for mounting an electronic part, a conductor pattern (7), and a heat-sink plate (6) arranged at the bottom of the mounting recess portion (1), characterized in that a conductor pattern (7) is formed on an insulating substrate (5);
a heat-sink plate (6) is adhered to a lower face of a portion of the insulating substrate (5) forming the mounting recess portion; and
a laser beam (2) is irradiated to an upper face of the portion (10) forming the mounting recess portion to form a mounting recess portion (1).

Abstract translation: 一种印刷线路板（3）的制造方法，该印刷线路板（3）包括用于安装电子部件的安装凹部（1），导体图案（7）和布置在安装凹部的底部的散热板（6） （1），其特征在于，在绝缘基板（5）上形成导体图案（7）。 散热板（6）粘附到形成安装凹部的绝缘基板（5）的一部分的下表面; 并且激光束（2）照射到形成安装凹部的部分（10）的上表面以形成安装凹部（1）。

公开(公告)号：EP1827068A2

公开(公告)日：2007-08-29

申请号：EP07075317.3

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (802) comprising an insulating substrate (806), a conductor pattern formed on a surface of the insulating substrate (806), a solder filling hole (801) passing through the insulating substrate (806) and arriving at an upper surface of the conductor pattern (851) and a solder (807) filled in the solder filling hole (801), characterized in that the insulating substrate (806) includes fibers (861) therein, and end portions (863) of the fibers (861) protrude from a wall face (810) of the solder filling hole (801) and encroach into the solder (807).

Abstract translation: 一种印刷电路板（802），包括绝缘基板（806），形成在所述绝缘基板（806）的表面上的导体图案，穿过所述绝缘基板（806）并到达所述绝缘基板 导体图案（851）的表面和填充在焊料填充孔（801）中的焊料（807），其特征在于，绝缘基板（806）包括纤维（861），纤维的端部（863） 861）从焊料填充孔（801）的壁面（810）突出并侵入焊料（807）。

公开(公告)号：EP0814643B1

公开(公告)日：2007-02-07

申请号：EP97109609.4

申请日：1997-06-12

Applicant: IBIDEN CO, LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00