公开(公告)号：EP2375879A1

公开(公告)日：2011-10-12

申请号：EP09834446.8

申请日：2009-12-22

Applicant: Sumitomo Bakelite Company Limited

Inventor： KATSURAYAMA, Satoru ,  MAEJIMA, Kenzou ,  FUJII, Tomoe

IPC: H05K3/34 ,  B32B27/00

CPC classification number: H05K3/305 ,  B32B5/142 ,  B32B27/08 ,  B32B27/281 ,  B32B27/286 ,  B32B27/288 ,  B32B27/302 ,  B32B27/304 ,  B32B27/308 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B2307/306 ,  B32B2307/546 ,  B32B2307/548 ,  B32B2307/714 ,  B32B2307/7246 ,  B32B2307/732 ,  B32B2457/00 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/036 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/3489 ,  H05K2201/0154 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/0195 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T156/1052 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/31504 ,  Y10T428/31721 ,  Y10T428/31725 ,  H01L2924/00

Abstract: A flexible substrate 10 of the present invention is the flexible substrate comprising a first resin film 1 having flux activity and a second resin film 2 different from the first resin film 1 laminated to said first resin film. The flexible substrate 10 is characterized in that the flexible substrate 10 is used by having a plurality of electronic components mounted on the surface of the first resin film 1, and thereafter having the respective electronic components and the flexible substrate 10 bonded at one time. The gel time of the first resin film 1 at 230°C is 100 seconds or more and 600 seconds or less.

Abstract translation: 本发明的柔性基板10是包含具有助焊剂活性的第一树脂膜1和与第一树脂膜1不同的第二树脂膜2的柔性基板10。 柔性基板10的特征在于，通过具有安装在第一树脂膜1的表面上的多个电子部件，然后一次接合各个电子部件和柔性基板10，来使用柔性基板10。 第一树脂膜1在230℃下的凝胶时间为100秒以上且600秒以下。

公开(公告)号：EP2353179A2

公开(公告)日：2011-08-10

申请号：EP09821348.1

申请日：2009-10-16

Applicant: Occam Portfolio LLC

Inventor： FJELSTAD, Joseph C.

IPC: H01L21/60

CPC classification number: H05K1/189 ,  H01L21/568 ,  H01L24/31 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/09481 ,  H05K2203/1316 ,  H05K2203/1469 ,  Y10T156/10 ,  Y10T156/1057 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an electronic assembly (400) and a method for its manufacture (800), (900, 1000 1200, 1400, 1500, and 1700). The assembly (400) uses no solder. Components (406) or component packages (402, 802, 804, 806) with I/O leads (412) are placed (800) onto a planar substrate (808). The assembly is encapsulated (900) with electrically insulating material (908) with vias (420, 1002) formed or drilled (1000) through the substrate (808) to the components' leads (412). Then the assembly is plated (1200) and the encapsulation and drilling process (1500) repeated to build up desired layers (422, 1502, 1702). The planar substrate (808) may be a flexible substrate (2016) allowing bending of an assembly (2000) to fit into various enclosures.

公开(公告)号：EP1659840A4

公开(公告)日：2010-03-03

申请号：EP05743245

申请日：2005-05-23

Applicant: IBIDEN CO LTD

Inventor： KAWAGUCHI KATSUO ,  FUTAMURA HIROFUMI ,  MIKADO YUKINOBU ,  ITO SOTAROU

IPC: H05K1/14 ,  H05K3/00 ,  H05K3/28 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/117 ,  H05K3/244 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09063 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2203/063 ,  Y10T29/49126

公开(公告)号：EP2007176A4

公开(公告)日：2009-11-11

申请号：EP07736883

申请日：2007-03-14

Applicant: SUMITOMO BAKELITE CO

Inventor： CHUMA TOSHIAKI ,  INABA MAKOTO

IPC: H05K1/14 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K1/148 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481

公开(公告)号：EP1909544A2

公开(公告)日：2008-04-09

申请号：EP07117380.1

申请日：2007-09-27

Applicant: NITTO DENKO CORPORATION

Inventor： Hu, Szu-Han ,  Ho, Voon Yee ,  Yamazaki, Hiroshi ,  McCaslin, Martin John

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0221 ,  H05K1/117 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/09809 ,  H05K2203/0733

Abstract: A wired circuit board has a plurality of insulating layers, a conductive layer having a signal wiring extending in a longitudinal direction which is covered with the insulating layers, and a signal connecting terminal provided on a longitudinal end of the signal wiring and exposed from the insulating layers, and a ground layer having a ground wiring covered with the insulating layers and formed to surround the signal wiring in a perpendicular direction to the longitudinal direction, and a ground connecting terminal provided on a longitudinal end of the ground wiring and exposed from the insulating layers. The signal connecting terminal and the ground connecting terminal are formed on an upper surface of the same insulating layer among the plurality of the insulating layers.

Abstract translation: 布线电路基板具有多个绝缘层，具有在长度方向上延伸的被绝缘层覆盖的信号布线的导电层，以及设置在信号布线的长度方向的一端并从绝缘层露出的信号连接端子 层和接地层，接地层具有覆盖有绝缘层的接地布线，并且形成为在与纵向方向垂直的方向上围绕信号布线;以及接地连接端子，设置在接地布线的纵向端并且从绝缘层暴露 层。 信号连接端子和接地连接端子形成在多个绝缘层中的相同绝缘层的上表面上。

公开(公告)号：EP1503216A4

公开(公告)日：2008-03-26

申请号：EP03758872

申请日：2003-10-24

Applicant: JSR CORP

Inventor： SATO KATSUMI ,  INOUE KAZUO

IPC: G01R31/02 ,  G01R1/06 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01B5/16 ,  H01L21/66 ,  H01L23/498 ,  H01R11/01 ,  H01R33/76 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R1/07314 ,  G01R1/06711 ,  G01R1/06733 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R11/01 ,  H01R12/523 ,  H05K1/116 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A sheet-form connector capable of forming an electrode structure having a small-diameter surface electrode unit, positively attaining a stable electric connection condition for a circuit device having electrodes formed at a small pitch, and providing a high durability without the electrode structure coming off an insulating sheet; and a production method and an application therefore. The sheet-form connector comprises an insulating sheet and a plurality of electrode structures provided to the insulating sheet to extend through the sheet in its thickness direction, wherein each of the electrode structures comprises a surface electrode part exposed to and protruding from the surface of the insulating sheet, a rear electrode part exposed to the rear surface of the insulating sheet, a shorting part extending continuously from the base end of the surface electrode part through the insulating sheet in its thickness direction until connected to the rear electrode part, and a holding part extending continuously from the base end of the surface electrode part along the surface of the insulating sheet toward the outer side.

公开(公告)号：EP1896861A2

公开(公告)日：2008-03-12

申请号：EP06785836.5

申请日：2006-06-28

Applicant: Teradyne, Inc.

Inventor： BEHZIZ, Arash ,  YAGHMAI, Roya

IPC: G01R31/28 ,  H05K3/46

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K3/3421 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10189 ,  Y10T29/49165

Abstract: In one embodiment, a laminated printed circuit board translator (100) is provided. In some embodiments, the translator includes a receiving board (110) adapted to receive a pin (55) , the receiving board includes a plated via (120) extending through the receiving board and has a hole (125) for receiving the pin. An interface board (130) laminated with the receiving board has a controlled depth via (160) extending through it to contact a conductive trace (140) . The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

公开(公告)号：EP1881751A1

公开(公告)日：2008-01-23

申请号：EP06731537.4

申请日：2006-04-10

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： ISEBO, Kazuhiro, Murata Manufacturing Co., Ltd

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/183 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ceramic multilayer substrate in which nonuniform deformation can be prevented without the addition of a particular process is provided.
The ceramic multilayer substrate includes a plurality of laminated ceramic layers and at least one conductor pattern 13 and 14 disposed on at least one of the ceramic layers. The ceramic multilayer substrate has a cavity 12 in at least a first main surface 10a. The ceramic multilayer substrate includes a deformation preventing pattern 15 disposed on at least one of the ceramic layers having an opening forming the cavity 12. The deformation preventing pattern 15 surrounds the entire perimeter of the opening and is formed of the same material as the conductor pattern.

Abstract translation: 提供一种其中可以防止不均匀变形而不加入特定工艺的陶瓷多层基板。 陶瓷多层基板包括多个层压陶瓷层和设置在至少一个陶瓷层上的至少一个导体图案13和14。 陶瓷多层基板在至少第一主表面10a中具有空腔12。 陶瓷多层基板包括设置在具有形成空腔12的开口的至少一个陶瓷层上的变形防止图案15.变形防止图案15围绕开口的整个周边并且由与导体图案相同的材料形成 。

公开(公告)号：EP1848254A2

公开(公告)日：2007-10-24

申请号：EP07006010.8

申请日：2007-03-23

Applicant: Würth Elektronik Rot am See GmbH & Co. KG

Inventor： Benjo, Andreas ,  Park, Heyje ,  Kostelnik, Jan

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/142 ,  F21K9/00 ,  H05K1/148 ,  H05K3/325 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2201/10409

Abstract: Die Erfindung schlägt ein Leiterplattenmodul vor, das eine Leiterplatte mit in der Leiterplatte angeordneten Leiterbahnen aufweist. An der Leiterplatte ist mindestens eine Verbindungseinrichtung ausgebildet, mit deren Hilfe diese Leiterplatte mit einer ähnlichen Leiterplatte direkt mechanisch und elektrisch verbunden werden kann, die eine gleiche oder ähnliche Verbindungseinrichtung aufweist. Das Leiterplattenmodul kann beispielsweise an einer Flachseite oder an einer Kante eine Leuchtdiode aufweisen, die durch in der Leiterplatte vorhandene Leiterbahnen mit Strom versorgt wird.

Abstract translation: 该模块具有印刷电路板和布置在印刷电路板中的导电路径。 连接装置 螺钉，设置在印刷电路板上，用于与包括相似连接装置的另一印刷电路板模块直接机械或电连接。 联接装置便于用于形成端模块的导电路径的电源的耦合。 LED（8）与导电路径连接。 还包括用于一组互连的印刷电路板的布置的独立权利要求。

公开(公告)号：EP1843391A1

公开(公告)日：2007-10-10

申请号：EP06811611.0

申请日：2006-10-11

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： KIMURA, Masahiro ,  SAITO, Yoshifumi

IPC: H01L23/12 ,  H01L25/00 ,  H01L25/04 ,  H01L25/18 ,  H05K1/14 ,  H05K3/46

CPC classification number: H05K1/141 ,  H01L23/15 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/284 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10477 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a state in which a multilayer electronic component including a resin layer disposed on a mounting board side is mounted on a mounting board, even when deformation, such as deflection and strain, occurs, a stress on the multilayer electronic component is relieved by this structure.
In a multilayer electronic component (1), ends (12, 13) of columnar conductors (8, 9) protrude from a main surface (14) of a resin layer (6) facing the outside. The multilayer electronic component (1) is mounted on a mounting board (2), and the ends (12, 13) of the columnar conductors (8, 9) are electrically connecting to conductive lands (26). In this case, a predetermined gap (31) is formed between the multilayer electronic component (1) and the mounting board (2).

Abstract translation: 在其中的状态的多层电子元件，包括设置在安装基板上侧的树脂层被安装在安装基板上，即使当变形，求作为偏转和应变的发生时，所述多层电子元件上的应力通过这种结构缓解 ， 在柱状导体的多层电子元件（1），端部（12，13）（8,9）从（6）的面向外侧的树脂层的一个主表面（14）突出。 层叠型电子元器件（1）被安装在安装板（2），和柱状导体的端部（12，13）（8,9）是导电的连接到焊盘（26）。 在这种情况下，一个预定的间隙（31）的层叠型电子元器件（1）和安装基板（2）之间形成的。