公开(公告)号：EP1814371A1

公开(公告)日：2007-08-01

申请号：EP07250254.5

申请日：2007-01-22

Applicant: Pace Micro Technology PLC

Inventor： Skow, Paul ,  Belford, James William ,  McGonigal, Colin

IPC: H05K3/34 ,  H01L23/488 ,  H01L23/367

CPC classification number: H05K3/341 ,  H01L2224/16225 ,  H05K1/0203 ,  H05K1/0268 ,  H05K1/111 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/10969 ,  H05K2203/162 ,  Y02P70/613

Abstract: A printed circuit board (PCB) is provided. The PCB has at least a first surface and a second surface. One or more pre-defined areas defined on the first surface comprise a PCB plane (8) for the location of one or more electrical components thereon. One or more test pads (18) provided on the second surface allow electrical testing of the solder connection between said PCB and/or one or more electrical components. Two or more connectivity points (10) are provided on the first surface in each of said pre-defined areas. The connectivity points are a spaced distance apart and are substantially electrically isolated from each other before soldering. The connectivity points are capable of electrical connection in case of sufficient solder being present between the PCB and the electrical component.

Abstract translation: 提供印刷电路板（PCB）。 PCB至少具有第一表面和第二表面。 限定在第一表面上的一个或多个预定义区域包括用于在其上定位一个或多个电气部件的PCB平面（8）。 设置在第二表面上的一个或多个测试焊盘（18）允许对所述PCB和/或一个或多个电气部件之间的焊料连接进行电气测试。 在每个所述预定义区域中的第一表面上提供两个或多个连接点（10）。 连接点是间隔开的距离，并且在焊接之前基本上彼此电隔离。 在PCB和电气部件之间存在足够的焊料的情况下，连接点能够电连接。

公开(公告)号：EP0959648B1

公开(公告)日：2007-03-14

申请号：EP98900160.7

申请日：1998-01-05

Applicant: IBIDEN CO., LTD.

Inventor： ISHIDA, Naoto ,  ASANO, Kouji

IPC: H05K1/14 ,  H05K3/36 ,  H01L23/12

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H05K3/308 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09481 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y02P70/613 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A printed wiring board comprising a circuit board (6) having a conductor circuit (5) and a through-hole (60), and a junction pin (1) inserted in the through-hole. The junction pin is made of a material which does not melt at a heating temperature in joining the junction pin to a counterpart pad (81). The junction pin includes a junction top portion (11) which is greater than the aperture diameter of the through-hole and becomes a junction part with the counterpart pad, and a leg portion (12) of a size enabling insertion into the through-hole. The leg portion is inserted in the through-hole and joined with the through-hole by a conductive material such as a solder material (20). In place of the junction pin, a junction ball of a substantially spherical shape may be joined by the conductive material.

公开(公告)号：EP1662778A1

公开(公告)日：2006-05-31

申请号：EP05257354.0

申请日：2005-11-30

Applicant: Psion Teklogix Systems Inc.

Inventor： Kricorissian, Gregg ,  Zhang, Tao

IPC: H04N5/225 ,  H05K1/14

CPC classification number: H04N5/2253 ,  H04N5/2256 ,  H05K1/116 ,  H05K1/144 ,  H05K3/3405 ,  H05K3/366 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/048 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10287 ,  H05K2201/2072 ,  H05K2203/128 ,  Y10T29/49144 ,  Y10T29/49169

Abstract: A method of constructing an image reader module and the image reader are described. The image reader module includes two or more circuit boards in a stacked configuration. Corresponding notches for receiving supports are formed along adjacent edges of the boards, which also have electrical contact points at the edges of each board connected to circuits on the boards. The supports are mounted in the notches between the two or more circuit boards to structurally interconnect the boards. Each of the supports, which may be flex cables or conductive bus bars, have one or more electrical conductors that are electrically connected to the contact points on the boards to electrically interconnect the boards, whereby the connections between the electrical conductors and the contact points form test points for the module. The notches may be substantially rectangular to receive the flex cable or may be slots to receive a bus bar. One end of the structural support flex cable or bus bar may be flush with one of the circuit boards and the other end of the structural support may extend past another one of the circuit boards. The supports may be soldered to the edges of the boards within the notches, which may be initially plated. In the image reader module an image sensor may be located on one of the circuit boards and an illumination assembly may be located on another of the circuit boards.

Abstract translation: 描述了构建图像读取器模块和图像读取器的方法。 图像读取器模块包括堆叠配置中的两个或多个电路板。 用于接收支撑件的相应凹口沿着板的相邻边缘形成，其在每个板的边缘处还具有连接到板上的电路的电接触点。 支撑件安装在两个或多个电路板之间的凹口中，以在板上结构互连。 可以是柔性电缆或导电母线的每个支撑件具有一个或多个电导体，其电连接到板上的接触点以电连接板，由此电导体和接触点之间的连接形成 测试点为模块。 凹口可以是基本上矩形的以接收柔性电缆，或者可以是用于接收汇流条的槽。 结构支撑柔性电缆或汇流条的一端可以与电路板中的一个齐平，并且结构支撑件的另一端可以延伸经过另一个电路板。 支撑件可以焊接到凹槽内的板的边缘，其可以最初被电镀。 在图像读取器模块中，图像传感器可以位于电路板中的一个上，并且照明组件可以位于另一个电路板上。

公开(公告)号：EP1536672A1

公开(公告)日：2005-06-01

申请号：EP03760945.0

申请日：2003-06-24

Applicant: NEC Corporation

Inventor： HASHIMOTO, Yoshiyuki ,  SATO, Junya

IPC: H05K1/14 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/368 ,  H05K3/305 ,  H05K3/325 ,  H05K2201/0314 ,  H05K2201/09481 ,  H05K2201/10393 ,  Y10T29/49126

Abstract: There is provided a structure for connecting substrates to each other, which is capable of thinning an electronic device on which a plurality of circuit boards is mounted, saving a space of the electronic device, and detaching a circuit board from the electronic device. The circuit board unit includes a first substrate 1 including, on a surface thereof, a first group of electrode terminals 10 arranged in a matrix, a second substrate 2 including, on a surface thereof, a second group of electrode terminals 20 arranged in a matrix in alignment with the first group of electrode terminals 10, and an anisotropic electrical conductor 3 sandwiched between the first and second substrates 10, 20. The first and second substrates 1, 2 and the anisotropic electrical conductor 3 are pressurized by means of a pressurizer 4 to electrically connect the electrode terminals 10 and 20 to each other through the anisotropic electrical conductor 3.

Abstract translation: 提供了一种用于将基板彼此连接的结构，其能够使其上安装有多个电路板的电子设备变薄，从而节省了电子设备的空间，并将电路板与电子设备分离。 电路基板单元包括第一基板1，第一基板1在其表面上包括以矩阵形式布置的第一组电极端子10，第二基板2在其表面上包括布置成矩阵的第二组电极端子20 与第一组电极端子10对准，以及夹在第一和第二基板10,20之间的各向异性电导体3.第一和第二基板1,2和各向异性导电体3通过加压器4 以通过各向异性电导体3将电极端子10和20彼此电连接

公开(公告)号：EP1484950A3

公开(公告)日：2005-05-25

申请号：EP04008025.1

申请日：2004-04-01

Applicant: Novar GmbH

Inventor： Gernhardt, Angelika ,  Goulet, Thomas ,  Menzel, Carsten ,  Ollik, Waldemar

IPC: H05K3/40 ,  H05K3/34

CPC classification number: H05K3/403 ,  H05K1/0284 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/42 ,  H05K2201/09118 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49789

Abstract: Ein Verfahren zur Kontaktierung der Leiterbahnen einer Schaltungsplatine (1) mit den Leiterbahnen eines Bauteiles (10) in MID-Technologie umfasst folgende Schritte: Auf dem Nutzen, aus dem die Schaltungsplatine gewonnen wird, werden die Leiterbahnen mindestens bis zum Rand der Schaltungsplatine geführt. Längs dieses Randes wird der Nutzen im Bereich der Leiterbahnen mit Durchgangsbohrungen (6d) versehen. Die Durchgangsbohrungen werden galvanisch durchkontaktiert. Die aus dem Nutzen herausgetrennte Schaltungsplatine wird relativ zu dem MID-Bauteil so positioniert, dass die aneinander grenzenden Leiterbahnen von Schaltungsplatine und MID-Bauteil miteinander verlötbar sind. Zweckmäßig erhält die Schaltungsplatine deckungsgleich zu den an ihrem Rand endenden Leiterbahnen rückseitig elektrische Kontaktierungsflächen (6b), welche über metallisierte und durchkontaktierte Bohrungen mit den vorderseitigen Leiterbahnen (5) elektrisch verbunden sind.

公开(公告)号：EP0843357B1

公开(公告)日：2003-07-30

申请号：EP97309161.4

申请日：1997-11-13

Applicant: TEXAS INSTRUMENTS INC.

Inventor： Abbott, Donald C.

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0554 ,  H05K2203/1394 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

公开(公告)号：EP1269807A1

公开(公告)日：2003-01-02

申请号：EP01914939.2

申请日：2001-03-30

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0195 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

Abstract: The invention comprises a method for manufacturing electrical connecting elements or semifinished products. Microvias are formed in a dielectric substrate layer by piercing a substrate layer (1) through a first conducting layer (3), which essentially covers an entire side of the substrate. The perforation depth (d) is at least equal to the total thickness of the substrate (1) and the first conducting layer (3). The conductor material of the first conducting layer (3) during the piercing step is deformed so that it partially covers the wall of the hole fabricated by the piercing process. The little remaining distance between the conductor material and the opposite side of the substrate layer can easily be bridged by plating the side of the first conducting layer (3) with additional conductor material. In this way, a reliable via contact is formed.

公开(公告)号：EP1196017A2

公开(公告)日：2002-04-10

申请号：EP01105764.3

申请日：2001-03-08

Applicant: Diehl Avionik Systeme GmbH

Inventor： Michling, Hans-Joachim ,  Gerstenberg, Bruno ,  Messmer, Helmut

IPC: H05K9/00 ,  H05K1/02

CPC classification number: H05K1/0233 ,  H03H2001/0014 ,  H05K1/0216 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0715 ,  H05K2201/09481 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/09972 ,  H05K2201/1003

Abstract: Die Erfindung betrifft eine Filteranordnung zur Trennung von HF-Energie und Signalenergie in einer Signalleitung (24). Die Signalleitung verläuft in einer ersten Lage (14) einer mehrlagigen Leiterkarte (10). In einer zweiten Lage (16) der Leiterkarte (10) ist eine Massefläche (34) angeordnet. Die zu filternde Signalleitung (24) ist in der ersten Lage (14) im Filterbereich (12) unterbrochen und wird in einer dritten Lage (18) weitergeführt, wobei sich die zweite und dritte Lage (16 bzw. 18) auf gegenüberliegenden Seiten der ersten Lage (14) befinden. Durch den Skineffekt wird sich die HF-Energie auf der Massefläche (34) zugewandte Seite der Signalleitung (24) konzentrieren. Die der Massefläche abgewandte Seite der Signalleitung (24) ist dann weitgehend von HF-Energie entkoppelt, so daß hier eine weitgehend von HF-Energie ungestörte Weiterführung des eigentlichen Signalweges erfolgen kann.

Abstract translation: 本发明涉及一种过滤器装置，用于在信号线（24）分离的RF能量和信号能量。 信号线中的多层印刷电路板（10）的第一层（14）延伸。 在该电路卡的第二层（16）（10）是接地平面（34）被布置。 该信号被滤波线（24）在过滤器区域（12）的第一层（14）中断，并且继续在第三层（18），其中，所述第二和第三层（16和18）在所述第一的相对侧 层（14）的位置。 由趋肤效应，面对所述信号线（24）的侧上的接地面（34）上的RF能量会集中。 从信号线（24）的接地面侧的背向然后很大程度上解耦的RF能量，使得可以发生实际的信号路径的很大程度上未受干扰的RF能量延续这里。

公开(公告)号：EP1173051A1

公开(公告)日：2002-01-16

申请号：EP00900913.5

申请日：2000-01-25

Applicant: Sony Chemicals Corporation

Inventor： Kurita, Hideyuki ,  Taniguchi, Masato

IPC: H05K1/14 ,  H05K3/36

CPC classification number: H05K3/361 ,  H05K3/305 ,  H05K3/323 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09709 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/0759

Abstract: In a flexible printed wiring board 10 obtained by connecting metal bumps 1a of a first flexible printed wiring part 1 and connection pads 2a of a second flexible printed wiring part 2, the first flexible printed wiring part 1 is composed of a conductive layer 4 and insulating layer 5 adjacent thereto, holes A being provided in the insulating layer 5 so as to reach the conductive layer 4, metal plugs 6 being formed in these holes A by an electrolytic plating method, metal bumps 1a being produced by making the tips of these metal plugs 6 project from the insulating layer 5. In this way, as many as possible flexible printed wiring boards can be obtained from a laminated sheet for flexible printed wiring of prescribed size.

Abstract translation: 在通过连接第一柔性印刷布线部分1的金属凸起1a和第二柔性印刷布线部分2的连接垫2a获得的柔性印刷布线板10中，第一柔性印刷布线部分1由导电层4和绝缘 与绝缘层5相邻设置的绝缘层5中的孔A通过电解电镀法形成在这些孔A中的金属插塞6，通过使这些金属的前端形成金属凸块1a， 插头6从绝缘层5突出。以这种方式，可以从具有规定尺寸的柔性印刷布线的层压片获得尽可能多的柔性印刷线路板。

公开(公告)号：EP1080615A1

公开(公告)日：2001-03-07

申请号：EP99930999.0

申请日：1999-05-03

Applicant: EPCOS AG

Inventor： STELZL, Alois ,  KRÜGER, Hans ,  WEIDNER, Karl ,  WOSSLER, Manfred

IPC: H05K3/18 ,  H05K3/24 ,  H05K3/42

CPC classification number: H05K3/403 ,  H01L21/4853 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H03H3/00 ,  H05K1/0243 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/245 ,  H05K3/3442 ,  H05K3/3473 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10083 ,  H05K2203/043 ,  H05K2203/1572 ,  H01L2224/81

Abstract: The invention relates to a multiple printed panel (1) which can be divided into individual printed panels (2) for electronic components (3), especially acoustic surface wave components. Each of these electronic components is suitable for contacting chips on the individual printed panels (2) using the flip-chip technique and for contacting the individual printed panels (2) with external connections using SMD technology. The inventive multiple printed panel (1) has metal-plated surfaces (5) for each individual printed panel (2), said metal-plated surfaces being located on a network which is integrated in the multiple printed panel and leads to a terminal pole (8). The bumps (13) are formed by galvanically separating metal onto the metal-plated surfaces (5).