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公开(公告)号:JP5282981B2
公开(公告)日:2013-09-04
申请号:JP2009546983
申请日:2008-10-20
申请人: 株式会社村田製作所
发明人: 優輝 伊藤
IPC分类号: H05K3/34
CPC分类号: H05K3/305 , H01L24/31 , H01L24/83 , H01L2224/29007 , H01L2224/2919 , H01L2224/29191 , H01L2224/83136 , H01L2224/83138 , H01L2224/8314 , H01L2224/83191 , H01L2224/83855 , H01L2224/8388 , H01L2224/83907 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15787 , H05K2201/10984 , H05K2203/0776 , Y02P70/613 , H01L2924/0715 , H01L2924/07025 , H01L2924/0635 , H01L2924/069 , H01L2924/00
摘要: Provided is a method for manufacturing an element mounting substrate wherein an element is simply and effectively fixed on a substrate. The method has a first step wherein an element (20), on which an adhesive layer (24) generating an adhesive force when heated is formed, and a substrate (10) are prepared; a second step of arranging the element (20) on the substrate (10); and a third step of bonding the adhesive layer (24) on the substrate (10) by heating and then cooling the adhesive layer in a state where the element (20) is arranged on the substrate (10). In the second step, after arranging a temporarily holding material (16) having fluidity on a part in a prescribed region on the substrate (10) whereupon the element (20) is to be arranged, the element (20) is arranged on the substrate (10) so that the adhesive layer (24) faces the substrate (10) by arranging a space (26) and that the element (20) is brought into contact with the temporarily holding material (16). In the third step, the temporarily holding material (16) disappears or is deformed by being heated, the space (26) between the adhesive layer (24) and the substrate (10) is eliminated to permit the adhesive layer (24) to be brought into contact with the substrate (10), and the adhesive layer (24) is bonded to the substrate (10).
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公开(公告)号:JPWO2009081648A1
公开(公告)日:2011-05-06
申请号:JP2009546983
申请日:2008-10-20
申请人: 株式会社村田製作所
IPC分类号: H01L21/52
CPC分类号: H05K3/305 , H01L24/31 , H01L24/83 , H01L2224/29007 , H01L2224/2919 , H01L2224/29191 , H01L2224/83136 , H01L2224/83138 , H01L2224/8314 , H01L2224/83191 , H01L2224/83855 , H01L2224/8388 , H01L2224/83907 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15787 , H05K2201/10984 , H05K2203/0776 , Y02P70/613 , H01L2924/0715 , H01L2924/07025 , H01L2924/0635 , H01L2924/069 , H01L2924/00
摘要: 簡単に効率よく素子を基板に固定することができる、素子搭載基板の製造方法を提供する。加熱されると粘着力を生じる接着層24が形成された素子20と、基板10とを用意する第1の工程と、基板10に素子20を配置する第2の工程と、基板10に素子20が配置された状態で加熱した後に冷却して、接着層24が基板10に接着される第3の工程とを備える。第2の工程において、素子20が配置されるべき基板10の所定領域の一部分に流動性を有する仮止め材16を配置した後、接着層24が空間26を設けて基板10に対向し、かつ素子20が仮止め材16に接するように、基板10に素子20を配置する。第3の工程において、仮止め材16が加熱されて消失又は変形して、接着層24と基板10との間の空間26がなくなって接着層24が基板10に接し、接着層24が基板10に接着される。
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公开(公告)号:JP4535002B2
公开(公告)日:2010-09-01
申请号:JP2006050475
申请日:2006-02-27
申请人: Tdk株式会社
CPC分类号: H01L23/5389 , H01L21/568 , H01L21/6835 , H01L23/5383 , H01L23/5384 , H01L23/544 , H01L24/24 , H01L24/25 , H01L24/82 , H01L2221/68368 , H01L2223/54473 , H01L2224/0401 , H01L2224/04105 , H01L2224/1134 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13171 , H01L2224/24225 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83132 , H01L2224/83136 , H01L2224/92244 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H05K1/185 , H05K3/4652 , H05K2201/09518 , H05K2201/09563 , H05K2201/096 , H05K2201/09781 , H05K2201/09918 , H05K2201/10674 , H05K2203/016 , H05K2203/1469 , H05K2203/166 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
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公开(公告)号:JPWO2008084843A1
公开(公告)日:2010-05-06
申请号:JP2008518534
申请日:2008-01-11
申请人: 積水化学工業株式会社
IPC分类号: C09J163/00 , C08G59/20 , C09J11/02 , C09J11/04 , C09J11/08 , C09J163/02
CPC分类号: H01L24/83 , C08G59/226 , C08G59/38 , C08L63/00 , C08L2666/22 , C09J163/00 , H01L24/29 , H01L2224/2919 , H01L2224/29198 , H01L2224/2929 , H01L2224/2939 , H01L2224/83136 , H01L2224/8385 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要: 本発明は、電子部品の間隔を一定に保って接合する際に用いられる電子部品用接着剤に関し、接合した電子部品間の距離を高精度に保ち、信頼性の高い電気装置を得ることができるとともに、ジェットディスペンス装置を用いた塗布を連続して安定的に行うことが可能な電子部品用接着剤を提供することを目的とする。本発明は、電子部品を接合するための電子部品用接着剤であって、CV値が10%以下であるスペーサー粒子と、繰り返し単位中に芳香環を有する10量体以下の分子構造を持ち、25℃で結晶性固体であり、かつ、50〜80℃の温度においてE型粘度計で測定した場合の粘度が1Pa・s以下であるエポキシ化合物(A)と、硬化剤とを含有する電子部品用接着剤である。
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公开(公告)号:JP2009194250A
公开(公告)日:2009-08-27
申请号:JP2008035164
申请日:2008-02-15
申请人: Honda Motor Co Ltd , 本田技研工業株式会社
IPC分类号: H01L27/00 , H01L21/02 , H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号: H01L24/12 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/06102 , H01L2224/13009 , H01L2224/13099 , H01L2224/1403 , H01L2224/14051 , H01L2224/2518 , H01L2224/81136 , H01L2224/81801 , H01L2224/83136 , H01L2225/06513 , H01L2225/06541 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01074 , H01L2924/01078 , H01L2924/01088 , H01L2924/04941 , H01L2924/07802 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要: PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent damage occurring at an electrical signal connecting portion effectively when a plurality of wafers are stuck, and can ensure excellent reliability and stabilized performance. SOLUTION: Electrical signal connecting portions 9, 26 are formed on the surface 30a, 30b of a wafer 1WA, 1WB which are stuck to another wafer, and the electrical signal connecting portions of one wafer are connected electrically with the electrical signal connecting portions of another wafer facing that wafer, wherein at least one of the electrical signal connecting portions 9 and 26 facing each other is formed to be protruded from the sticking surface 30a, 30b, and reinforcing protrusions 5b, 9b and 26b are formed to be protruded from the sticking surface 30a, 30b with heights equal to or higher than that of the protruding connecting portion, while being insulated from a semiconductor circuit, in a region on the sticking surface 30a, 30b where the protruding connecting portion is formed but the electrical signal connecting portions 9, 26 are not arranged, thus obtaining a semiconductor device. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译: 要解决的问题:提供一种可以在多个晶片被卡住时有效地防止在电信号连接部分发生损坏的半导体器件,并且可以确保优异的可靠性和稳定的性能。 解决方案:电信号连接部分9,26形成在晶片1WA,1WB的表面30a,30b上,粘合在另一个晶片上,并且一个晶片的电信号连接部分与电信号连接 面对该晶片的另一个晶片的部分形成为彼此面对的电信号连接部9和26中的至少一个从粘贴表面30a,30b突出,并且加强突起5b,9b和26b形成为突出 在与突出的连接部分的高度等于或高于突出连接部分的粘着表面30a,30b的同时与半导体电路绝缘的情况下,在形成突出连接部分的粘附表面30a,30b上的区域中, 连接部分9,26不被布置,从而获得半导体器件。 版权所有(C)2009,JPO&INPIT
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公开(公告)号:JPWO2007034764A1
公开(公告)日:2009-03-26
申请号:JP2007536480
申请日:2006-09-19
申请人: パナソニック株式会社
IPC分类号: G06K19/077 , G06K19/07 , H01L21/60
CPC分类号: G06K19/07749 , G06K19/0775 , H01L21/6835 , H01L23/49855 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/31 , H01L24/83 , H01L2223/6677 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/13012 , H01L2224/13144 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/26165 , H01L2224/274 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/8114 , H01L2224/81191 , H01L2224/81903 , H01L2224/83136 , H01L2224/8314 , H01L2224/83192 , H01L2224/83851 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01061 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/1902 , H01L2924/30105 , H01L2924/30107 , H01Q1/22 , H01Q9/16 , H01L2224/13099 , H01L2924/00 , H01L2224/05599
摘要: 少なくとも情報を記憶する機能を有する半導体ICチップ(30)と、外部機器と信号の交信を行うためのアンテナパターン(14)が形成された樹脂基板(10)とを備え、この樹脂基板(10)上のアンテナパターン(14)の一端部に設けられたアンテナ端子(141)とICチップ(30)の電極端子(22)とが対向するように実装され、かつアンテナパターン(14)とICチップ(30)の回路形成面(20)との間に少なくとも5μmのギャップ規制用絶縁層(32)を設けた構成からなる。
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公开(公告)号:JP2008198909A
公开(公告)日:2008-08-28
申请号:JP2007034625
申请日:2007-02-15
申请人: Elpida Memory Inc , エルピーダメモリ株式会社
IPC分类号: H01L25/065 , H01L25/07 , H01L25/18
CPC分类号: H01L25/0657 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/04026 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/49052 , H01L2224/4909 , H01L2224/49175 , H01L2224/49431 , H01L2224/49433 , H01L2224/73265 , H01L2224/83136 , H01L2224/83192 , H01L2224/8385 , H01L2224/8592 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/07802 , H01L2924/10162 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要: PROBLEM TO BE SOLVED: To provide a semiconductor package with laminated semiconductor chips, capable of preventing bonding defects or the like without lowering the degree of freedom of the arrangement of an electrode pad.
SOLUTION: The semiconductor package comprises: a package substrate 10 provided with a plurality of connection terminals 11 on the surface; the semiconductor chip 100 provided with a plurality of bonding pads 101 on the surface; a plurality of bonding wires 102h and 102l for respectively connecting the plurality of connection terminals 11 and the plurality of bonding pads 101; a resin 103 formed so as to fill a gap between the bonding wires 102h and 102l and the surface of the semiconductor chip 100; and the semiconductor chip 200 provided on the bonding wires 102h and 102l through a film-like resin 203. At least three bonding wires 102h of the plurality of bonding wires 102h and 102l are formed at the almost same height and to be higher than the other bonding wires 102l.
COPYRIGHT: (C)2008,JPO&INPIT摘要翻译: 要解决的问题:为了提供具有层叠半导体芯片的半导体封装,能够防止接合缺陷等而不降低电极焊盘的布置的自由度。 解决方案:半导体封装包括:在表面上设置有多个连接端子11的封装基板10; 半导体芯片100在表面上设置有多个接合焊盘101; 用于分别连接多个连接端子11和多个接合焊盘101的多个接合线102h和102l; 形成为填充接合线102h和1021之间的间隙的树脂103和半导体芯片100的表面; 以及通过膜状树脂203设置在接合线102h和102l上的半导体芯片200.多个接合线102h和102l中的至少三个接合线102h形成在几乎相同的高度并且高于另一个 接合线1021。 版权所有(C)2008,JPO&INPIT
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公开(公告)号:JP2008066610A
公开(公告)日:2008-03-21
申请号:JP2006244964
申请日:2006-09-11
申请人: Hitachi Ltd , 株式会社日立製作所
发明人: FUJIWARA SHINICHI , HARADA MASAHIDE , YOSHINARI HIDETO , ISHIHARA SHOSAKU , YAMASHITA SHIRO , YOSHIDA ISAMU , IKEDA UKYO
IPC分类号: H01L23/48
CPC分类号: H01L23/3735 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/83 , H01L24/84 , H01L24/92 , H01L2224/26165 , H01L2224/26175 , H01L2224/291 , H01L2224/29111 , H01L2224/33181 , H01L2224/371 , H01L2224/37147 , H01L2224/3754 , H01L2224/40095 , H01L2224/40225 , H01L2224/40499 , H01L2224/73263 , H01L2224/83136 , H01L2224/83139 , H01L2224/8314 , H01L2224/83385 , H01L2224/83801 , H01L2224/83815 , H01L2224/84801 , H01L2224/84815 , H01L2224/9221 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/1305 , H01L2924/13055 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/84
摘要: PROBLEM TO BE SOLVED: To suppress the displacement of a semiconductor device and a lead relative to the upper surface of a thermal diffusion plate at the time of solder reflow in a semiconductor module comprising the semiconductor device having a lower surface connected to the upper surface of the thermal diffusion plate by solder and an upper surface connected to a lead by solder. SOLUTION: A semiconductor module comprises a first conductive film and a second conductive film which are formed on the principal plane of a mounting substrate separately from each other, a thermal diffusion plate connected to the upper surface of the first conductive film by solder, a semiconductor device connected to the upper surface of the thermal diffusion plate by solder, and a lead whose one end and the other end are connected to the second conductive film and the semiconductor device by solder, respectively. On the periphery of a joining region to which the semiconductor device is connected by solder on the upper surface of the thermal diffusion plate, a projecting portion projecting from the joining region is formed. The rotation of a semiconductor chip in the upper surface of the thermal diffusion plate in a solder connection process is prevented by the projecting portion. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译: 要解决的问题:为了抑制半导体组件中的半导体模块中的焊料回流时半导体器件和引线相对于热扩散板的上表面的位移,该半导体模块具有连接到 通过焊料使热扩散板的上表面和通过焊料与铅连接的上表面。 解决方案:半导体模块包括彼此分开形成在安装基板的主平面上的第一导电膜和第二导电膜,热扩散板,通过焊料连接到第一导电膜的上表面 通过焊料连接到热扩散板的上表面的半导体器件,以及一端和另一端分别通过焊料与第二导电膜和半导体器件连接的引线。 在热扩散板的上表面上通过焊料将半导体器件连接到的接合区域的周边,形成从接合区域突出的突出部。 通过突出部防止焊料连接工序中的热扩散板的上表面中的半导体芯片的旋转。 版权所有(C)2008,JPO&INPIT
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公开(公告)号:JP4035447B2
公开(公告)日:2008-01-23
申请号:JP2002588631
申请日:2002-05-08
申请人: 新電元工業株式会社
发明人: 昌明 冨田
IPC分类号: H01L29/41 , H01L21/336 , H01L23/485 , H01L23/488 , H01L23/492 , H01L23/495 , H01L23/498 , H01L29/417 , H01L29/74 , H01L29/78 , H01L29/87
CPC分类号: H01L24/02 , H01L23/488 , H01L23/492 , H01L23/49562 , H01L23/49844 , H01L24/01 , H01L24/33 , H01L24/37 , H01L24/40 , H01L29/41716 , H01L29/74 , H01L29/87 , H01L2224/26145 , H01L2224/27013 , H01L2224/291 , H01L2224/32014 , H01L2224/32245 , H01L2224/371 , H01L2224/37599 , H01L2224/40137 , H01L2224/73253 , H01L2224/83136 , H01L2224/83801 , H01L2224/84801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01058 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/12036 , H01L2924/1301 , H01L2924/13033 , H01L2924/13034 , H01L2924/13055 , H01L2924/13091 , H01L2924/16152 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要: The present invention has an object of providing a thyristor-type semiconductor device and a manufacturing method for the same which can prevent, even when conventional manufacturing equipment is used, the electrode terminals 13, 14 from being provided in a significantly tilted state where the electrode terminals 13, 14 are in contact with the silicon substrate 20, and can also prevent the electrode terminals 13, 14 from being provided in a state where the electrode terminals 13, 14 come into contact with the silicon substrate 20, even when there are warping and undulations in the silicon substrate 20. In a semiconductor device of the present invention, the supports 11a, 11b are provided on both surfaces of the silicon substrate 20 using a glass material. When doing so, the support 11b is disposed in a part of the boundary between the second N-type layer 18 and the second P-type layer 19 that is opposite the side surface 22. With this structure, even if the electrode terminals 13, 14 are tilted when the electrode terminals 13, 14 are provided, the supports 11a, 11b support the electrode terminals 13, 14 from below, so that the electrode terminals 13, 14 can be prevented from being provided in contact with the silicon substrate 20. Also, even when there are warping and undulations in the silicon substrate 20, the electrode terminals 13, 14 can be prevented from being provided in contact with the silicon substrate 20.
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10.
公开(公告)号:JP2005514846A
公开(公告)日:2005-05-19
申请号:JP2003559014
申请日:2002-12-11
发明人: ホフマン クリスティアン , クリューガー ハンス , ポルトマン ユルゲン
IPC分类号: H01L23/12 , H01L29/06 , H03H3/02 , H03H3/06 , H03H3/08 , H03H9/02 , H03H9/05 , H03H9/10 , H03H9/25 , H03H9/56
CPC分类号: H03H9/1078 , H01L24/31 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/11334 , H01L2224/16225 , H01L2224/16237 , H01L2224/291 , H01L2224/29111 , H01L2224/73203 , H01L2224/83136 , H01L2224/83951 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01068 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/0132 , H01L2924/0133 , H01L2924/09701 , H01L2924/10157 , H01L2924/12042 , H01L2924/1517 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H03H9/059 , H01L2924/0105 , H01L2224/13111 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要: 構成素子を簡単かつ確実にカプセル化するため、チップと支持体基板との間の接続部を、板部接続を用いて形成することが提案される。 この接続部は支持体基板の上にある切欠部に降下される。 ここで構成素子は支持体基板の上に直接載置する。 とりわけチップ上の構成素子構造体を取り囲むフレームの上に載置する。
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