公开(公告)号：US07205485B2

公开(公告)日：2007-04-17

申请号：US10831247

申请日：2004-04-23

申请人： Chin-Tien Chiu ,  Chin-Huang Chang ,  Chih-Ming Huang

发明人： Chin-Tien Chiu ,  Chin-Huang Chang ,  Chih-Ming Huang

IPC分类号： H05K1/16

CPC分类号： H05K3/305 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/0187 ,  H05K2201/09072 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49146

摘要： A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.

摘要翻译： 提供一种印刷电路板及其制造方法。 制备具有芯层和其上的多对接合焊盘的衬底，其中在每对接合焊盘之间的芯层上形成有至少一个开口。 焊接掩模层覆盖芯层并填充开口，其中凹陷部分形成在焊料掩模层固化期间在开口上的焊料掩模层的位置处。 当将小的无源部件安装在印刷电路板上时，在无源部件的底部和焊料掩模层的凹部之间形成空间。 封装树脂可以流入空间，以在接合焊盘之间形成绝缘屏障，以防止接合焊盘之间的桥接和无源部件的短路。

公开(公告)号：US06835897B2

公开(公告)日：2004-12-28

申请号：US10309564

申请日：2002-12-04

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Cheng-Lun Liu

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Cheng-Lun Liu

IPC分类号： H05K103

CPC分类号： H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2203/1572 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A warpage preventing substrate is provided. A plurality of first and second conductive traces are respectively formed on a first surface and a second surface of a core layer of the substrate, each conductive trace having a terminal, and a plurality of first and second non-functional traces are respectively formed on the first and second surfaces of the core layer at area free of the conductive traces. The first non-functional traces are arranged in different density from the second non-functional traces in a manner that, stress generated from the first conductive traces and first non-functional traces counteracts stress generated from the second conductive traces and second non-functional traces, to thereby prevent warpage of the substrate and maintain flatness of the substrate.

公开(公告)号：US07266888B2

公开(公告)日：2007-09-11

申请号：US11043496

申请日：2005-01-25

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09663 ,  H05K2201/09781 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/4916 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

摘要翻译： 提供了一种制造防翘曲电路板的方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电绝缘性电路板的表面上， 绝缘芯层在没有导电迹线的区域处，其中相邻的虚拟电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。

公开(公告)号：US06864434B2

公开(公告)日：2005-03-08

申请号：US10441647

申请日：2003-05-19

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  H05K1/03

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09663 ,  H05K2201/09781 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/4916 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

摘要翻译： 提供了一种防翘曲电路板及其制造方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电气绝缘电路板的表面上 - 绝缘芯层在没有导电迹线的区域处，其中相邻的虚设电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。

公开(公告)号：US20050145413A1

公开(公告)日：2005-07-07

申请号：US11043496

申请日：2005-01-25

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  H05K1/03 ,  H05K1/00 ,  H05K3/02

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09663 ,  H05K2201/09781 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/4916 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

摘要翻译： 提供了一种防翘曲电路板及其制造方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电气绝缘电路板的表面上 - 绝缘芯层在没有导电迹线的区域处，其中相邻的虚设电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。

公开(公告)号：US06737737B1

公开(公告)日：2004-05-18

申请号：US10355610

申请日：2003-01-31

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

IPC分类号： H01L23495

CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

摘要翻译： 提供一种具有芯片支撑构件的半导体封装，包括具有管芯焊盘和多个引线的引线框架，以及安装在管芯焊盘的中心部分的芯片支撑构件。 芯片支撑构件具有附接到管芯焊盘的第一表面和相对的第二表面。 至少芯片安装在芯片支撑部件的第一表面上，以通过芯片支撑部件将芯片与芯片焊盘隔开，以防止芯片被CTE引起的热应力（热膨胀系数 ）芯片和引线框架之间的不匹配，从而消除分层，翘曲和芯片裂纹。 此外，插入在芯片和芯片焊盘之间的芯片支撑构件提供了更大的灵活性，用于在芯片焊盘上安装各种尺寸或形状的芯片，而不必使用对应于芯片焊盘轮廓的芯片。

公开(公告)号：US20150115479A1

公开(公告)日：2015-04-30

申请号：US14399495

申请日：2012-05-07

申请人： Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

发明人： Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/75 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A laminating device (230) and method are disclosed for laminating semiconductor die (220) on substrates on a panel (200) of substrates. The laminating device (230) includes lamination units (234,236,238,240) that operate independently of each other so that a row or column of semiconductor die (220) may be independently laminated onto a row or column of substrates simultaneously.

摘要翻译： 公开了用于将基板上的半导体管芯（220）层压在基板（200）上的层压装置（230）和方法。 层压装置（230）包括层叠单元（234,236,238,240），其彼此独立地操作，使得半导体管芯（220）的行或列可以独立地层压到基板的行或列上。

公开(公告)号：US20120081860A1

公开(公告)日：2012-04-05

申请号：US13129510

申请日：2010-10-04

申请人： Itzhak Pomerantz ,  Shiv Kumar ,  Robert Miller ,  Chin-Tien Chiu ,  Peng Fu ,  Cheeman Yu ,  Hem Takiar ,  Chih Chiang Tung ,  Kaiyou Qian

发明人： Itzhak Pomerantz ,  Shiv Kumar ,  Robert Miller ,  Chin-Tien Chiu ,  Peng Fu ,  Cheeman Yu ,  Hem Takiar ,  Chih Chiang Tung ,  Kaiyou Qian

IPC分类号： H05K1/14 ,  B32B3/10 ,  B32B3/02 ,  H05K7/00 ,  B32B3/30

CPC分类号： H05K5/0252 ,  G06K19/07 ,  Y10T428/239 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24802

摘要： A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.

摘要翻译： 公开了一种记录装置，其包括至少一个预处理表面的表面，以便更好地粘附在表面上的墨。 存储器件的表面可以通过用激光在表面上刻划线或者通过用粒子喷射器形成离散的变形来预处理。 在封装过程中，通过在模板上提供粗糙图案也可以使表面粗糙化。 在另外的实施例中，表面可以被化学预处理以使表面粗糙化和/或增加表面的粘附能。

公开(公告)号：US07967184B2

公开(公告)日：2011-06-28

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US20100052155A1

公开(公告)日：2010-03-04

申请号：US12614945

申请日：2009-11-09

申请人： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

发明人： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

IPC分类号： H01L23/04

CPC分类号： G06K19/077 ,  B29C45/14311 ,  B29C45/14647 ,  B29C2045/14327 ,  G06K19/07724 ,  G06K19/07732 ,  H01L23/10 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

摘要翻译： 公开了一种闪存卡及其制造方法。 卡包括制造成接收单面或双面盖的半导体封装。 半导体封装的表面可以形成有孔，沟槽和/或戳记。 在形成孔，沟和/或标记之后，可以在注射成型工艺中将盖子附接到包装表面。 在注射成型过程中，熔融的塑料流入与半导体封装的表面互连的孔，沟槽和/或戳痕。 因此，当熔融塑料硬化时，孔，沟槽和/或戳痕确保盖保持牢固地附接到半导体封装。