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    ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE
    91.
    发明申请
    ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE 审中-公开
    防腐结构选择性地与保护环结构集成

    公开(公告)号：US20080029844A1

    公开(公告)日：2008-02-07

    申请号：US11462070

    申请日：2006-08-03

    Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  William R. Tonti

    Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  William R. Tonti

    IPC: H01L29/00

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.

    Abstract translation: 用于制造抗熔丝结构的反熔丝结构和相关方法包括半导体衬底内的掺杂阱。 暴露掺杂阱的第一孔径和第二孔径位于位于半导体衬底和掺杂阱上方的电介质层内。 第一导体层位于第一孔内，第二导体层位于第二孔内。 至少第一反熔丝材料层接触第一导体层。 第一导体层和第二导体层可以包括掺杂的导体材料，其在抗熔丝结构融合时提供抗熔丝二极管或抗熔丝电阻器。

    Pixel sensor having doped isolation structure sidewall
    92.
    发明授权
    Pixel sensor having doped isolation structure sidewall 有权
    具有掺杂隔离结构侧壁的像素传感器

    公开(公告)号：US07141836B1

    公开(公告)日：2006-11-28

    申请号：US10908885

    申请日：2005-05-31

    Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    IPC: H01L27/148

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.

    Abstract translation: 形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成隔离结构。 隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。 用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。 替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

    Multiple threshold voltage FET using multiple work-function gate materials
    94.
    发明授权
    Multiple threshold voltage FET using multiple work-function gate materials 失效
    多阈值电压FET采用多功能栅极材料

    公开(公告)号：US06448590B1

    公开(公告)日：2002-09-10

    申请号：US09695199

    申请日：2000-10-24

    Applicant: James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    Inventor： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    IPC: H01L2710

    CPC classification number: H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

    Abstract translation: 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

    Multiple precipitation doping process
    95.
    发明授权
    Multiple precipitation doping process 失效
    多重沉淀掺杂工艺

    公开(公告)号：US06300228B1

    公开(公告)日：2001-10-09

    申请号：US09386089

    申请日：1999-08-30

    Applicant: James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    Inventor： James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    IPC: H01L2122

    CPC classification number: H01L21/268 ,  H01L21/0455 ,  H01L21/2255

    Abstract: A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.

    Abstract translation: 用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。 通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。 然后将衬底（30）退火。 退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。 退火过程也使非晶区域（32）半导体材料结晶。 基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。 掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

    Process for defining a pattern using an anti-reflective coating and structure therefor
    96.
    发明授权
    Process for defining a pattern using an anti-reflective coating and structure therefor 失效
    使用抗反射涂层定义图案的方法及其结构

    公开(公告)号：US06030541A

    公开(公告)日：2000-02-29

    申请号：US100542

    申请日：1998-06-19

    Applicant: James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

    Inventor： James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

    IPC: H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/033

    CPC classification number: H01L21/0276 ,  H01L21/28123 ,  H01L21/32139

    Abstract: A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.

    Abstract translation: 通过在表面上提供硬掩模材料来限定表面中的图案; 在所述硬掩模材料上沉积抗反射涂层; 在抗反射涂层上施加光致抗蚀剂层; 图案化光致抗蚀剂层，抗反射层和硬掩模材料; 并除去光致抗蚀剂层和抗反射层的剩余部分; 然后使用硬掩模作为掩模来图案化衬底。 还提供了一种用于在表面上限定图案的结构，其包括其上具有硬掩模材料的表面; 位于硬掩模材料上的抗反射涂层; 以及位于抗反射涂层上的光致抗蚀剂。 还提供了用于除去硬掩模材料的蚀刻剂组合物，其包含HF和氯的水性组合物。

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