公开(公告)号：US06326284B1

公开(公告)日：2001-12-04

申请号：US08610488

申请日：1996-03-04

申请人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

发明人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

IPC分类号： H01L2176

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/76202 ,  H01L29/518

摘要： A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.

摘要翻译： 通过在基板上形成氧化膜而制造的半导体装置，在惰性气氛中，在800℃以上的温度下进行氧化膜的热处理，接着是用于形成晶体管的常规步骤，由于 松弛在氧化膜或衬底表面产生的应力。

公开(公告)号：US06204155B1

公开(公告)日：2001-03-20

申请号：US09597985

申请日：2000-06-19

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

公开(公告)号：US5643805A

公开(公告)日：1997-07-01

申请号：US401678

申请日：1995-03-10

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L23/4855 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/135

摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

摘要翻译： 具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜 通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

公开(公告)号：US5537884A

公开(公告)日：1996-07-23

申请号：US287593

申请日：1994-08-08

申请人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

发明人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

IPC分类号： G01N3/00 ,  G01N3/24 ,  G01N19/04

CPC分类号： G01N3/24 ,  G01N19/04 ,  G01N2203/0066 ,  G01N2203/0091

摘要： A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.

公开(公告)号：US20110140185A1

公开(公告)日：2011-06-16

申请号：US13032009

申请日：2011-02-22

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近，在这些端子处，凸起电极 （208）。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US20070241330A1

公开(公告)日：2007-10-18

申请号：US11808808

申请日：2007-06-13

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07247879B2

公开(公告)日：2007-07-24

申请号：US10873360

申请日：2004-06-23

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L29/04

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07138722B2

公开(公告)日：2006-11-21

申请号：US11057495

申请日：2005-02-15

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US07057283B2

公开(公告)日：2006-06-06

申请号：US10825436

申请日：2004-04-16

申请人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

发明人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/3157 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3114 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06102 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2924/01034

摘要： A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide α-ray shielding of the semiconductor device.

摘要翻译： 一种半导体装置，其中可以在没有任何底部填充的情况下进行倒装芯片接合，并且其包括半导体器件，通过掩模印刷含有颗粒的电绝缘材料在半导体器件上形成的电绝缘层，以及形成在电学上的外部连接端子 绝缘层并与半导体器件的电极电连接。 电绝缘层形成为具有提供半导体器件的α射线屏蔽的厚度。

公开(公告)号：US07013564B2

公开(公告)日：2006-03-21

申请号：US09971566

申请日：2001-10-09

申请人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

发明人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

IPC分类号： H01R43/00 ,  H05K13/00

CPC分类号： H05K1/181 ,  B23K1/0016 ,  B23K35/004 ,  B23K35/007 ,  B23K35/262 ,  B23K2101/40 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/532 ,  H01L24/29 ,  H01L2224/83101 ,  H01L2924/01322 ,  H01L2924/15747 ,  H05K3/3426 ,  H05K3/3463 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T428/12708 ,  Y10T428/12715 ,  H01L2924/00

摘要： A method of producing an electronic device by connecting a lead of a semiconductor device with an electrode of a circuit board to form a bonded structure. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

摘要翻译： 一种通过将半导体器件的引线与电路板的电极连接以形成接合结构来制造电子器件的方法。 在接合结构中，通过Sn-Bi合金层将无铅Sn-Ag-Bi合金焊料施加到电极。 Sn-Bi合金优选含有1〜20重量％的Bi，以获得良好的焊料润湿性。 为了获得本发明中具有较高可靠性的理想的接合特性，在Sn-Bi合金层下方设置有铜层，从而获得足够的接合强度。