公开(公告)号：US06459144B1

公开(公告)日：2002-10-01

申请号：US09973611

申请日：2001-10-09

申请人： Han-Ping Pu ,  Shih-Kuang Chiu ,  Keng-Yuan Liao ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Shih-Kuang Chiu ,  Keng-Yuan Liao ,  Chien-Ping Huang

IPC分类号： H01L23495

CPC分类号： H01L23/3128 ,  H01L23/4334 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

摘要翻译： 提出了一种倒装芯片半导体封装，其中，堤坝结构由围绕芯片的基板上的诸如环氧树脂的粘合剂化合物形成。 粘合剂化合物的热膨胀系数比基板的热膨胀系数大，并且在制造冷却过程中产生较大的热收缩力，以抵消基板的热应力，从而保持基板和芯片的平面性和结构完整性 。 此外，芯片可以以将非活性表面暴露于大气中以便于散发由芯片产生的热量的方式制造，同时可以在芯片上另外设置散热器，从而进一步改善热量 耗散半导体封装的效率。

公开(公告)号：US06184573B2

公开(公告)日：2001-02-06

申请号：US09310727

申请日：1999-05-13

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01079

摘要： The invention provides a chip package, particularly a dual-chip package, that is featured by directly connecting a lead frame to at least a chip included therein, and is specifically featured by directly connecting the inner leads of a lead frame to the bumps formed on at least two chips included therein.

摘要翻译： 本发明提供了一种芯片封装，特别是双芯片封装，其特征在于将引线框架直接连接到其中包括的至少一个芯片，并且具体地是将引线框架的内部引线直接连接到形成在 其中包括至少两个芯片。

公开(公告)号：US08680663B2

公开(公告)日：2014-03-25

申请号：US13342751

申请日：2012-01-03

申请人： Yu-Feng Chen ,  Han-Ping Pu

发明人： Yu-Feng Chen ,  Han-Ping Pu

IPC分类号： H01L23/02

CPC分类号： H01L23/02 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed.

摘要翻译： 封装结构封装的方法和装置。 一种结构包括第一集成电路封装，其包括安装在第一基板上的至少一个集成电路器件，从封装连接器上的多个封装，其从底表面延伸并且以一个或多个行的图案布置， 第一底物; 以及第二集成电路封装，其包括安装在第二基板上的至少另一个集成电路器件和耦合到封装连接器上的多个封装的上表面上的多个焊盘，以及从所述第二基板的底表面延伸的多个外部连接器 第二基板; 其中外部连接器的图案与包装连接器上的包装图案交错，使得包装连接器上的包装件不与外部连接器垂直对准。 公开了形成结构的方法。

公开(公告)号：US20130187277A1

公开(公告)日：2013-07-25

申请号：US13443556

申请日：2012-04-10

申请人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Chih-Hang Tung ,  Kai-Chiang Wu ,  Ming-Che Ho

发明人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Chih-Hang Tung ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L23/488 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings.

摘要翻译： 半导体管芯包括在凸块下金属化（UBM）层上的裂纹阻挡层。 裂缝止动器为具有至少两个开口的中空圆筒形状。

公开(公告)号：US20130175705A1

公开(公告)日：2013-07-11

申请号：US13348449

申请日：2012-01-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

IPC分类号： H01L23/52 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.

摘要翻译： 提供了用于包装的应力补偿，以及形成方法。 应力补偿层从集成电路管芯放置在衬底的相对侧上。 应力补偿层被设计成抵抗基板的模具侧上的应力施加结构中的至少一些，例如由至少部分地封装第一集成电路管芯的模制化合物施加的应力。 封装还可以电耦合到衬底。

公开(公告)号：US20130127040A1

公开(公告)日：2013-05-23

申请号：US13302059

申请日：2011-11-22

申请人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

发明人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

IPC分类号： H01L23/485 ,  B23K1/00 ,  B23K1/20 ,  B23K31/12

CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012

摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

摘要翻译： 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

公开(公告)号：US08288871B1

公开(公告)日：2012-10-16

申请号：US13095185

申请日：2011-04-27

申请人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

摘要翻译： 凹凸跟踪（BOT）结构及其在芯片上的布局的实施例减少了金属焊盘上的电介质层和BOT结构的金属迹线上的应力。 通过将金属凸块的轴线定位成远离金属轨迹，可以减小应力，这可以降低金属迹线从基板和电介质层与金属垫分层的危险。 此外，金属焊盘和金属迹线上的电介质层的应力也可以通过将金属迹线的轴线朝向芯片的中心定向而减小。 结果，可以提高收率。

公开(公告)号：US20120119354A1

公开(公告)日：2012-05-17

申请号：US12944453

申请日：2010-11-11

申请人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Ming-Song Sheu ,  Yu-Ling Tsai ,  Chen-Shien Chen ,  Han-Ping Pu

发明人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Ming-Song Sheu ,  Yu-Ling Tsai ,  Chen-Shien Chen ,  Han-Ping Pu

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L23/48

CPC分类号： H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/563 ,  H01L23/295 ,  H01L23/562 ,  H01L24/32 ,  H01L24/743 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81191 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/10156 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2924/00

摘要： A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

摘要翻译： 模具具有第一表面，与第一表面相对的第二表面，并且侧壁包括第一部分和第二部分，其中第一部分比第二部分更靠近第一表面。 圆角接触模具的侧壁的第一部分并且环绕模具。 工件通过焊料凸块与模具结合，第二表面面向工件。 第一底部填充物填充模具和工件之间的间隙，其中第一底部填充物接触圆角，并且其中第一底部填充物和圆角由不同的材料形成。

公开(公告)号：US07932601B2

公开(公告)日：2011-04-26

申请号：US12899168

申请日：2010-10-06

申请人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

发明人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

摘要翻译： 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US07871860B1

公开(公告)日：2011-01-18

申请号：US12620321

申请日：2009-11-17

申请人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

发明人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

IPC分类号： H01L21/00 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/46

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L2224/73203 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供芯片和基板。 该方法还包括将芯片接合到衬底。 该方法还包括在粘合芯片之后，在芯片和基板之间分配密封材料。 根据该方法，将芯片和基板保持在从接合芯片到分配密封材料的温度范围内，并且其中温度范围的下限约为室温的两倍。