公开(公告)号：US06635970B2

公开(公告)日：2003-10-21

申请号：US10068537

申请日：2002-02-06

申请人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

发明人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

摘要翻译： 片上芯片模块及相关的形成方法。 第一和第二半导体芯片被耦合在一起。 第一芯片包括分别在第一芯片的第一和第二侧上的第一布线层和第一导电基板。 电源电压VDD适于电耦合到第一芯片的第二侧。 第二芯片包括分别在第二芯片的第一和第二侧上的第二布线层和第二导电基板。 接地电压GND适于电耦合到第二芯片的第二侧。 第一芯片的第一侧电耦合到第二芯片的第一侧。 电源电压VDD和接地电压GND适于为第一和第二芯片提供电力。

公开(公告)号：US06265771B1

公开(公告)日：2001-07-24

申请号：US09238492

申请日：1999-01-27

申请人： Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

发明人： Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

IPC分类号： H01L2310

CPC分类号： H01L23/4334 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An apparatus for simultaneously removing heat from two surfaces of a semiconductor structure includes a heat sink mounted to a front surface and a heat sink mounted to a back surface of the semiconductor structure. The structure can be two chips mounted in face-to-face arrangement, and the heat sinks remove heat from back surfaces of both chips.

摘要翻译： 同时从半导体结构的两个表面去除热量的装置包括安装到前表面的散热器和安装到半导体结构的后表面的散热片。 该结构可以是以面对面布置安装的两个芯片，并且散热器从两个芯片的背面去除热量。

公开(公告)号：US08298917B2

公开(公告)日：2012-10-30

申请号：US12423254

申请日：2009-04-14

申请人： Paul S. Andry ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L23/544

CPC分类号： H01L21/78

摘要： A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches.

摘要翻译： 一种方法包括接收具有前侧和后侧的至少一个晶片，其中前侧在其上具有多个集成电路芯片。 晶片的背面变薄，从晶片的背面去除材料图案以形成多个切割沟槽。 每个切割槽位于对应于多个芯片中的每一个的边缘的晶片正面的位置。 切割槽填充有填充材料，并且切割支撑件附接到晶片的前侧。 从切割槽移除填充材料，并且将力施加到切割支撑件，以将晶片上的多个芯片中的每一个沿着切割沟槽彼此分离。

公开(公告)号：US20120193790A1

公开(公告)日：2012-08-02

申请号：US13444193

申请日：2012-04-11

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/498

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US20110161682A1

公开(公告)日：2011-06-30

申请号：US12650516

申请日：2009-12-30

申请人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

发明人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3287 ,  Y02D10/171

摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.

摘要翻译： 电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。 第一调节器模块耦合到第一接口和第二接口。 第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。 向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。 接收的功率被调节以在第二电压下产生功率。 将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。 处理器接口向处理器的多个逻辑组的逻辑组递送电力。

公开(公告)号：US07786596B2

公开(公告)日：2010-08-31

申请号：US12038501

申请日：2008-02-27

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

公开(公告)号：US07741231B2

公开(公告)日：2010-06-22

申请号：US12056773

申请日：2008-03-27

申请人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/31

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20100025857A1

公开(公告)日：2010-02-04

申请号：US12181467

申请日：2008-07-29

申请人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

发明人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC分类号： H01L23/48 ,  G06F9/45

CPC分类号： H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

摘要翻译： 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

公开(公告)号：US20090315188A1

公开(公告)日：2009-12-24

申请号：US12550494

申请日：2009-08-31

申请人： Brent Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Brent Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L23/488 ,  H01L23/48

CPC分类号： H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

摘要翻译： 提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括用一层掩埋氧化物结合到硅衬底结构的硅晶片载体结构和分离这些硅结构的氮化物层。 在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。 通孔填充有多晶硅或导电材料的填充材料。 然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。 当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。 然后通孔用导电材料回填。

公开(公告)号：US20090140404A1

公开(公告)日：2009-06-04

申请号：US12038501

申请日：2008-02-27

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： H01L23/10

CPC分类号： H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

摘要翻译： 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。