公开(公告)号：US20120018851A1

公开(公告)日：2012-01-26

申请号：US12840688

申请日：2010-07-21

申请人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.

摘要翻译： 提供了由于背面平坦化处理而对金属污染免疫的贯穿衬底通孔（TSV）结构。 在形成贯穿衬底通孔（TSV）沟槽之后，扩散阻挡衬里共形沉积在TSV沟槽的侧壁上。 通过在扩散阻挡衬里的垂直部分上沉积介电材料形成电介质衬垫。 通过随后填充TSV沟槽形成金属导电通孔结构。 去除扩散阻挡衬里的水平部分。 扩散阻挡衬里通过阻挡源自金属导电通路结构的残余金属材料进入衬底的半导体材料来保护衬底的半导体材料，从而保护衬底内的半导体器件免受金属污染。

公开(公告)号：US20110180920A1

公开(公告)日：2011-07-28

申请号：US12695312

申请日：2010-01-28

申请人： Mukta G. Farooq ,  John A. Fitzsimmons

发明人： Mukta G. Farooq ,  John A. Fitzsimmons

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29014 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

摘要翻译： 组件可以包括微电子元件，例如具有其中制造的电路和半导体器件的半导体元件，以及多个电连接器，例如附接到微电子元件的触点的焊球。 连接器可以被可压缩介电材料的第一内部区域200和介电材料的第二外部区域包围。 在一个实施例中，底部填充物可以在相应的连接器或第二区域之间接触微电子元件的面。 第二区域可以提供约束力，使得在连接器的体积膨胀期间，第一区域可以抵抗第二区域的约束力而被压缩。

公开(公告)号：US07955955B2

公开(公告)日：2011-06-07

申请号：US11746684

申请日：2007-05-10

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L21/301

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US20100314711A1

公开(公告)日：2010-12-16

申请号：US12194211

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L27/12 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。 提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。 第一有源电路层晶片比另一个晶片低成本。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US07819376B2

公开(公告)日：2010-10-26

申请号：US11930269

申请日：2007-10-31

申请人： David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

发明人： David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/27334 ,  H01L2224/73104 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

摘要翻译： 用于在晶片的附接点上形成互连的方法包括以下步骤：提供具有预定形状的多个空腔的模具，在空腔的表面上沉积脱模剂，用互连材料填充空腔以形成互连， 从模具中除去脱模剂，以及将互连件附接到晶片的附接点。 除了剥离层之外，还可任选地沉积粘合剂层。 粘合剂层可以用于例如将芯片粘合到包装上。

公开(公告)号：US20100163949A1

公开(公告)日：2010-07-01

申请号：US12344697

申请日：2008-12-29

申请人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

发明人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

摘要翻译： 包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件 区域位于半导体衬底上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

公开(公告)号：US20100139958A1

公开(公告)日：2010-06-10

申请号：US12706418

申请日：2010-02-16

申请人： Mukta G. Farooq ,  Charles C. Goldsmith

发明人： Mukta G. Farooq ,  Charles C. Goldsmith

IPC分类号： H05K1/09

CPC分类号： B23K3/0638 ,  B23K2101/40 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49149

摘要： Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solders are heated to a temperature above a melting point of the Pb-free solder joint for a sufficient time to allow complete melting of both the Pb-free solder joints and Pb-containing solder paste and the homogenous mixing thereof during assembly. These molten materials mix together such that the Pb from the Pb-containing solder disperses throughout substantially the entire Pb-free solder joint for complete homogenization of the molten materials to form the homogenous hybrid interconnect structures of the invention.

摘要翻译： 具有混合互连栅格阵列的形成和组装方法，其由印刷电路板的相应位置上的无铅焊点和含Pb焊膏的均匀混合物组成。 将排列的无铅焊点和含Pb焊料加热到无铅焊点的熔点以上的温度足够的时间，以使无铅焊点和含Pb焊膏完全熔化 并在组装期间均匀混合。 这些熔融材料混合在一起，使得来自含Pb焊料的Pb分散在基本上整个无铅焊料接头处，以使熔融材料完全均化，形成本发明的均匀混合互连结构。

公开(公告)号：US20100038777A1

公开(公告)日：2010-02-18

申请号：US12190173

申请日：2008-08-12

申请人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

发明人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

摘要翻译： 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

公开(公告)号：US20100019354A1

公开(公告)日：2010-01-28

申请号：US12573364

申请日：2009-10-05

申请人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

IPC分类号： H01L23/58 ,  H01L23/544

CPC分类号： H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

摘要翻译： 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

公开(公告)号：US07622737B2

公开(公告)日：2009-11-24

申请号：US11776114

申请日：2007-07-11

申请人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

IPC分类号： H01L23/58 ,  H01L21/00

CPC分类号： G01R31/2853 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012

摘要： Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

摘要翻译： 提供电气检测BEOL故障的测试结构。 在一个实施例中，该结构包括：输入/输出连接，其布置在嵌入绝缘体中的主导电垫上方; 设置在绝缘体上的电介质层; 主通孔延伸穿过介电层到主导电焊盘，用于在输入/输出连接和主导电焊盘之间提供电连接; 以及填充有与所述输入/输出连接电连接的导电材料的次级通孔，所述次级通孔延伸穿过所述电介质层到与所述主导电焊盘绝缘的次级导电焊盘电连接的次互连。