公开(公告)号：US5910641A

公开(公告)日：1999-06-08

申请号：US895537

申请日：1997-07-17

申请人： Michael A. Gaynes ,  Jaynal A. Molla

发明人： Michael A. Gaynes ,  Jaynal A. Molla

IPC分类号： H01L21/60 ,  H01L23/373 ,  H05K3/20 ,  H05K3/32 ,  H05K3/42 ,  H01L23/02

CPC分类号： H01L24/83 ,  H01L23/3733 ,  H01L24/29 ,  H05K3/323 ,  H05K3/423 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H05K2201/10378 ,  H05K2203/0307 ,  H05K2203/0726 ,  H05K3/205

摘要： An electrically conductive adhesive film having a pattern of microscopic elongate metal particles which extend from one surface to the other to provide an interconnection between confronting conductive metal pads abutting the surface. The particles have sharp ends to penetrate the oxide coating on the conductive metal pads of an electronic module when force is applied to press the module against the film.

摘要翻译： 一种导电粘合剂膜，其具有从一个表面延伸到另一个表面的微观细长金属颗粒的图案，以提供邻接表面的相对的导电金属垫之间的互连。 当施加力以将模块压靠在膜上时，颗粒具有尖端以穿透电子模块的导电金属焊盘上的氧化物涂层。

公开(公告)号：US5779870A

公开(公告)日：1998-07-14

申请号：US422510

申请日：1995-04-13

申请人： D. Eric Seip

发明人： D. Eric Seip

IPC分类号： C25D7/06 ,  H05K3/02 ,  H05K3/06 ,  H05K3/38 ,  H05K3/46 ,  C25D1/04

CPC分类号： H05K3/384 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/0522 ,  H05K2203/068 ,  H05K2203/0723 ,  H05K2203/0726 ,  H05K3/064 ,  H05K3/385 ,  H05K3/46 ,  H05K3/4611

摘要： Drum or smooth side-treated metal foil can be used either as an intermediate product for use in the manufacture of laminate or as a part of the finished laminate to be used in the manufacture of multi-layer printed circuit board (PCB) packages. By treating the drum or smooth side of metal foil with a bond strength enhancer rather than treating the matte side or rough side, or both sides, several time-consuming and costly steps can be bypassed in the manufacture of multi-layer printed circuit boards (PCB) while the integrity of the metal foil, -laminate and multi-layer PCB are not compromised and are actually enhanced by way of improved impedance control and adhesion characteristics after relamination. This novel foil can be initially bonded to substrate on either side before circuit formation and can be used either as an internal foil layer or as a foil cap. The invention includes methods of manufacture of the metal foil, laminate and multi-layer printed circuit board. A variation of the invention involves a component or tool for use in manufacturing articles such as printed circuit boards. The component is a temporary laminate constructed of one or more sheets of drum-side-treated copper foil mounted on a sheet of aluminum. The copper foil, which, in a finished printed circuit board, will constitute a functional element, has a drum-side, which has been subjected to an adhesion-promoting treatment, and a rough side, which has not been subject to the adhesion-promoting treatment. The sheet of aluminum constitutes a discardable or reusable element. Either surface (treated drum-side or untreated matte side) of each copper sheet can be bonded to the aluminum, depending on which embodiment of the basic invention is being used. The side of the copper foil not bonded to the aluminum will be bonded to the resin in the next step.

摘要翻译： 鼓或光滑的侧面处理的金属箔可以用作制造层压板或作为用于制造多层印刷电路板（PCB）封装的成品层压板的一部分的中间产品。 通过用粘合强度增强剂处理滚筒或光滑的金属箔侧，而不是处理无光泽面或粗糙面或两面，在制造多层印刷电路板时可以绕过几个耗时且昂贵的步骤（步骤 PCB），而金属箔，层压板和多层PCB的完整性不受影响，实际上通过改进的阻抗控制和再粘合后的粘附特性得到增强。 这种新颖的箔可以在电路形成之前的任一侧初始地结合到衬底上，并且可以用作内部箔层或箔盖。 本发明包括金属箔，叠层和多层印刷电路板的制造方法。 本发明的变型涉及用于制造诸如印刷电路板的制品的部件或工具。 该部件是由安装在铝板上的一个或多个鼓侧处理的铜箔构成的临时层压体。 在成品印刷电路板中将构成功能元件的铜箔具有已经进行增粘处理的鼓侧，并且没有经受粘合增强处理的粗糙面， 促进治疗。 铝板构成了可废弃或可重复使用的元件。 根据使用的基本发明的实施方案，每个铜片的任一表面（经处理的鼓侧或未处理的无光泽面）可以结合到铝上。 未结合到铝的铜箔的侧面将在下一步中与树脂结合。

公开(公告)号：US5647966A

公开(公告)日：1997-07-15

申请号：US537512

申请日：1995-10-02

申请人： Eiichi Uriu ,  Osamu Makino ,  Hironobu Chiba ,  Chisa Yokota

发明人： Eiichi Uriu ,  Osamu Makino ,  Hironobu Chiba ,  Chisa Yokota

IPC分类号： H01F17/00 ,  H01F41/04 ,  H05K1/03 ,  H05K3/20 ,  C25D1/00

CPC分类号： H01F41/042 ,  H05K3/205 ,  H01F17/0006 ,  H05K1/0306 ,  H05K2203/0117 ,  H05K2203/0726 ,  H05K3/4629

摘要： A method for producing a conductive pattern includes the steps of forming a mask layer on a conductive base plate, the mask layer having a pattern defining an exposed area of the conductive base plate; forming a conductive pattern on the exposed area of the conductive base plate by electroforming using a plating liquid which substantially maintains the pattern of the mask layer; and transferring the conductive pattern onto a support layer without removing the mask layer.

摘要翻译： 制造导电图案的方法包括以下步骤：在导电基板上形成掩模层，掩模层具有限定导电基板的暴露区域的图案; 通过使用基本上保持掩模层的图案的电镀液进行电铸而在导电基板的暴露区域上形成导电图案; 并且将导电图案转移到支撑层上而不去除掩模层。

公开(公告)号：US5646068A

公开(公告)日：1997-07-08

申请号：US384506

申请日：1995-02-03

申请人： Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

发明人： Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H01L23/498 ,  H01L25/065 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L25/0652 ,  H05K3/3473 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0726

摘要： A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.

摘要翻译： 一种制造微电子电路的方法及其连接图案包括以下步骤：提供衬底（3），优选硅，并且优选地包括在其上的金层（36）下方的一层镍（38）。 区域形成在基板上，用于使用第一冶金将电气部件连接到基板，优选金和凸起图案（5,7）由不同于第一冶金，优选铅/锡焊料的第二冶金形成。 在与至少一个凸块和至少一个焊盘接触的衬底上形成互连图案。 焊料凸块的图案通过提供优惠券（31）并且在附件上图案化凸起并施加到基板上而形成，然后加热以使凸块流到基板上。 然后从凸块上取出试样，凸块残留在基片上。 电气部件应用于第一冶金领域，并通过引线接合或磁带自动键合技术进行电接合。 电气部件被施加到第二冶金的区域并通过倒装芯片技术电连接。

公开(公告)号：US5440805A

公开(公告)日：1995-08-15

申请号：US127975

申请日：1993-09-27

申请人： Robert C. Daigle ,  W. David Smith ,  John A. Olenick ,  David J. Arthur ,  Gwo S. Swei

发明人： Robert C. Daigle ,  W. David Smith ,  John A. Olenick ,  David J. Arthur ,  Gwo S. Swei

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K3/20 ,  H05K3/24 ,  H05K3/28 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

CPC分类号： H05K3/4632 ,  H01L21/4857 ,  H01L23/49894 ,  H01L23/5383 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4647 ,  H05K3/4682 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0289 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/09563 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K3/20 ,  H05K3/243 ,  H05K3/28 ,  H05K3/328 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4658 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： In accordance with the present invention, a circuit assembly is manufactured in an additive process using at least one layer of a fluoropolymer composite material and a conductive material. The conductive layers are plated, and the fluoropolymer composite layers are laminated. The use of the filled fluoropolymeric composite eliminates the need for a barrier metal layer between the insulation and the conductors. A plurality of these circuit assemblies are stacked, one on top of the other. At least, selected exposed locations of the conductive material comprise a diffusible conductive material (e.g., gold). Once stacked the circuit assemblies are subjected to lamination under heat and pressure to simultaneously fuse adjacent fluoropolymer composite material and diffuse adjacent diffusible conductive material together to form an integral multilayer circuit having solid conductive interconnects.

摘要翻译： 根据本发明，使用至少一层含氟聚合物复合材料和导电材料的添加工艺制造电路组件。 对导电层进行电镀，层压含氟聚合物复合层。 使用填充的氟聚合物复合材料消除了在绝缘体和导体之间的阻挡金属层的需要。 多个这些电路组件一个在另一个之上堆叠。 至少，导电材料的选定的暴露位置包括可扩散的导电材料（例如金）。 一旦堆叠，电路组件在热和压力下进行层压以同时熔化相邻的含氟聚合物复合材料并将相邻的可扩散导电材料扩散在一起以形成具有固体导电互连的整体多层电路。

公开(公告)号：US5426850A

公开(公告)日：1995-06-27

申请号：US983342

申请日：1992-11-30

申请人： Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

发明人： Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

IPC分类号： H05K3/04 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46 ,  H05K3/06

CPC分类号： H05K3/428 ,  H05K3/205 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/04 ,  H05K3/4652 ,  H05K3/4658 ,  Y10S29/016 ,  Y10T29/49156 ,  Y10T29/49158

摘要： A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.

摘要翻译： 通过以下步骤制造布线板：（A）在由第一金属制成的细长载体金属箔的一侧上形成具有与第一金属的蚀刻条件不同的第二金属的薄层; （B）在所述薄层的表面上形成与蚀刻条件不同于所述第二金属的第三金属的期望布线图案; （C）将所述载体金属箔叠置在所述布线图案的一侧位于绝缘基板上，由此将所述布线图案嵌入所述绝缘基板中; 和（D）在其所需部分刻蚀载体金属箔和薄层。

公开(公告)号：US5403672A

公开(公告)日：1995-04-04

申请号：US59658

申请日：1993-05-12

申请人： Naoyuki Urasaki ,  Kouichi Tsuyama ,  Kiyoshi Hasegawa ,  Shuichi Hatakeyama ,  Akinari Kida ,  Akishi Nakaso ,  Hiroshi Nomura

发明人： Naoyuki Urasaki ,  Kouichi Tsuyama ,  Kiyoshi Hasegawa ,  Shuichi Hatakeyama ,  Akinari Kida ,  Akishi Nakaso ,  Hiroshi Nomura

IPC分类号： H05K3/02 ,  H05K3/06 ,  H05K3/38 ,  B32B15/20 ,  B32B3/30

CPC分类号： H05K3/025 ,  H05K3/062 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0723 ,  H05K2203/0726 ,  H05K3/383 ,  Y10S428/935 ,  Y10T29/49155 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/1291 ,  Y10T428/12993

摘要： A metal foil for printed wiring boards comprising a first copper layer to be adhered to a resin, a second copper layer having a sufficient strength as a metal layer and a nickel-phosphorus alloy layer containing 1.1% by weight or more of phosphorus formed between the first and second copper layers is suitable for producing printed wiring boards having excellent heat resistance, particularly during production procedures.

摘要翻译： 一种用于印刷电路板的金属箔，包括要粘附到树脂上的第一铜层，具有足够强度作为金属层的第二铜层和含有1.1重量％以上的磷的镍 - 磷合金层， 第一和第二铜层适用于制造具有优异耐热性的印刷电路板，特别是在制造过程中。

公开(公告)号：US5333379A

公开(公告)日：1994-08-02

申请号：US863904

申请日：1992-04-06

申请人： Hiroshi Odaira ,  Yoshizumi Sato

发明人： Hiroshi Odaira ,  Yoshizumi Sato

IPC分类号： B29C33/14 ,  B29C44/18 ,  B29C45/14 ,  B29L31/34 ,  H05K1/02 ,  H05K3/00 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  B29C67/22 ,  H05K3/30

CPC分类号： H05K3/205 ,  B29C44/18 ,  H05K3/0014 ,  H05K2201/09118 ,  H05K2203/0726 ,  Y10T29/4913 ,  Y10T29/49146

摘要： Small projections are arranged on a molding surface of at least one of an upper die half and a lower die half constituting a molding die, and a predetermined number of conductor circuits each including small projections are formed on the molding surface by electrically plating. A predetermined number of conductor circuits are formed on the molding surface of other die half in the same manner. Subsequently, the molding surfaces of both the die halves are brought in pressure contact with each other so that the electrically plated layers each including small projections on the molding surface are connected electrically. Thereafter, the hollow space between both the die halves is filled with a predetermined resin, whereby the conductor circuits are reversely secured to the resultant molded product to complete production of a three-dimensional wiring board. After electronic components are assembled on the three-dimensional wiring board, the resin is removed from the molded product by dissolving the resin. Consequently, a hollow three-dimensional wiring structure is formed. Thus, three-dimensional conductor circuits which are electrically connected to each other at predetermined positions are formed on the front and rear surfaces of molded product. Thus, the three-dimensional wiring board can be produced at a high efficiency without any necessity for complicated steps and actuation. An electronic circuit module produced by assembling electronic components on the three-dimensional wiring board assures that signals can be processed at a high speed.

摘要翻译： 在构成成型模具的上模半模和下模半部中的至少一个的成形面上配置有小突起，通过电镀在成形面上形成规定数量的具有小突起的导体电路。 以相同的方式在其他半模的成型表面上形成预定数量的导体电路。 随后，两个半模的成型表面彼此压力接触，使得在成型表面上各包括小突起的电镀层电连接。 此后，两个半模之间的中空空间填充有预定的树脂，由此导体电路与所得模制产品反向固定，从而完成三维布线板的制造。 将电子元件组装在三维布线板上之后，树脂通过溶解树脂而从成形品中除去。 因此，形成中空的三维布线结构。 因此，在模制品的前表面和后表面上形成在预定位置彼此电连接的三维导体电路。 因此，可以高效率地制造三维接线板，而不需要复杂的步骤和致动。 通过在三维布线板上组装电子部件而制造的电子电路模块确保能够高速地处理信号。

公开(公告)号：US5326412A

公开(公告)日：1994-07-05

申请号：US994801

申请日：1992-12-22

申请人： Christopher M. Schreiber ,  Haim Feigenbaum

发明人： Christopher M. Schreiber ,  Haim Feigenbaum

IPC分类号： H05K3/20 ,  H05K3/28 ,  H05K3/40 ,  B32B31/12

CPC分类号： H05K3/4007 ,  B32B37/12 ,  B32B38/1833 ,  H05K3/205 ,  B32B2457/08 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/0117 ,  H05K2203/063 ,  H05K2203/0726 ,  H05K3/281 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

摘要： A corrosion resistant barrier is provided for isolated circuity. An isolated circuit (10, 12) with raised interconnection features (16, 18) having a corrosion resistant gold coating (34) is formed on a reusable stainless steel mandrel (22) which is provided with indentations to define raised features. A seed layer (32) of copper is electroplated on the mandrel in a pattern of the isolated circuit to be formed. The copper seed layer (32) is then followed by electroplated layers of gold (34), nickel (36) and copper (38) until a total desired conductor thickness is achieved. A dielectric substrate (44, 46) is laminated on the multilayer conductive traces of the circuit. After removal of the multilayer circuit from the mandrel, a predrilled dielectric coverlay (50) is laminated to the circuit with holes in the coverlay receiving the raised circuit features (52). The finished part is then etched to remove the copper seed layer from the raised features.

摘要翻译： 隔离电路提供了耐腐蚀屏障。 在可重复使用的不锈钢心轴（22）上形成具有具有耐腐蚀金涂层（34）的具有凸起的互连特征（16,18）的隔离电路（10,12），所述不锈钢心轴（22）设有压痕以限定凸起特征。 铜芯的种子层（32）以待形成的隔离电路的图案在心轴上电镀。 铜籽晶层（32）之后是金（34），镍（36）和铜（38）的电镀层，直到达到总的所需导体厚度。 电介质基板（44,46）层压在电路的多层导电迹线上。 在从心轴移除多层电路之后，预先填充的电介质覆盖层（50）被层压到电路上，其中覆盖层中的孔接收升高的电路特征（52）。 然后蚀刻成品部分以从凸起的特征​​中去除铜种子层。

公开(公告)号：US5262247A

公开(公告)日：1993-11-16

申请号：US982689

申请日：1992-11-30

申请人： Toshiyuki Kajiwara ,  Yoshinori Tanii ,  Kazuhiko Hashimoto

发明人： Toshiyuki Kajiwara ,  Yoshinori Tanii ,  Kazuhiko Hashimoto

IPC分类号： H05K3/02 ,  H05K3/38 ,  B32B15/20

CPC分类号： H05K3/025 ,  H05K2201/0338 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/0723 ,  H05K2203/0726 ,  H05K3/382 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/12611 ,  Y10T428/1291 ,  Y10T428/12993

摘要： A thin copper foil for a printed wiring board comprising a copper foil supporter having a surface with a roughness; a parting payer consisting of chrome compound; a thin copper foil layer formed on the parting layer which will be attached to a board as printed wiring. A copper-nickel compound metal layer is interposed between the parting layer and the thin copper foil layer, wherein said copper-nickel compound metal layer is formed to be integral with the thin copper foil layer with a peel strength therebetween such that said copper-nickel compound metal layer will be left on the thin copper layer when the parting layer with the copper foil supporter is peeled off.

摘要翻译： 一种用于印刷线路板的薄铜箔，包括具有粗糙表面的铜箔支撑件; 由铬化合物组成的分离付款人; 形成在分离层上的薄铜箔层，其将作为印刷线路附接到板。 在分离层和薄铜箔层之间插入铜 - 镍复合金属层，其中所述铜 - 镍复合金属层形成为与薄铜箔层成一体，其间具有剥离强度，使得所述铜 - 镍 当剥离具有铜箔支撑体的分离层时，复合金属层将留在薄铜层上。