公开(公告)号：US09418978B2

公开(公告)日：2016-08-16

申请号：US14828244

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/485 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L25/065 ,  H01L21/3105 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/31051 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/48

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract translation: 封装封装（PoP）结构包括第一封装和第二封装。 第一包装包括第一模具，第二模具和芯材料。 芯材料具有第一表面和第二表面。 第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。 第一模具设置在第一表面和第二表面之间的芯材料中。 第二管芯耦合到第一RDL和第二RDL之一。 第二包装包括第三管芯和插入件。 插入器具有第一侧和第二侧。 第三裸片耦合到插入器的第二侧。 第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

公开(公告)号：US20150357320A1

公开(公告)日：2015-12-10

申请号：US14828244

申请日：2015-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/31051 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/48

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract translation: 封装封装（PoP）结构包括第一封装和第二封装。 第一包装包括第一模具，第二模具和芯材料。 芯材料具有第一表面和第二表面。 第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。 第一模具设置在第一表面和第二表面之间的芯材料中。 第二管芯耦合到第一RDL和第二RDL之一。 第二包装包括第三管芯和插入件。 插入器具有第一侧和第二侧。 第三裸片耦合到插入器的第二侧。 第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

公开(公告)号：US12243837B2

公开(公告)日：2025-03-04

申请号：US18231032

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US12209013B2

公开(公告)日：2025-01-28

申请号：US18365997

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhao-Yi Wang ,  Chin-Yu Ku ,  Wen-Hsiung Lu ,  Lung-Kai Mao ,  Ming-Da Cheng

IPC: B81C1/00 ,  B81B3/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

公开(公告)号：US20240290656A1

公开(公告)日：2024-08-29

申请号：US18655989

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20240258266A1

公开(公告)日：2024-08-01

申请号：US18629670

申请日：2024-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai Jun Zhan ,  Chin-Fu Kao ,  Kuang-Chun Lee ,  Ming-Da Cheng ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/16 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81203

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

公开(公告)号：US12051622B2

公开(公告)日：2024-07-30

申请号：US17112119

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/60

CPC classification number: H01L21/76877 ,  H01L21/4825 ,  H01L21/76802 ,  H01L23/53228 ,  H01L24/14 ,  H01L2021/60022

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US12033883B2

公开(公告)日：2024-07-09

申请号：US17805557

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Ming-Da Cheng

IPC: H01L21/683 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L21/6835 ,  H01L21/2885 ,  H01L21/486 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

公开(公告)号：US20240222194A1

公开(公告)日：2024-07-04

申请号：US18604691

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US12027435B2

公开(公告)日：2024-07-02

申请号：US17818742

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L23/5384 ,  H01L24/81

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.