公开(公告)号：US20020100913A1

公开(公告)日：2002-08-01

申请号：US10014398

申请日：2001-12-14

Inventor： Yoshimi Uda ,  Kazuya Ishiwata ,  Shinsaku Kubo ,  Yasuyuki Watanabe

IPC: H01L033/00

CPC classification number: H05K1/0271 ,  H01J29/02 ,  H01J31/127 ,  H01J2329/0489 ,  H01J2329/861 ,  H05K1/092 ,  H05K3/248 ,  H05K2201/035 ,  H05K2201/09745 ,  H05K2203/0514 ,  Y10T29/49147 ,  Y10T29/49174 ,  Y10T29/53204 ,  Y10T29/53209

Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 nullm. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.

Abstract translation: 作为具有微细线且能够抑制基板中的裂纹产生和细线剥离的基板，本发明公开了一种在细线上布置多个凹槽的结构，特别是其中多个 凹槽不超过200毫米。 还公开了沿着与细线的长度方向交叉的方向配置多个凹部的结构。

公开(公告)号：US06426154B1

公开(公告)日：2002-07-30

申请号：US09668747

申请日：2000-09-25

Applicant: Takayuki Naba ,  Hiroshi Komorita ,  Noritaka Nakayama ,  Kiyoshi Iyogi

Inventor： Takayuki Naba ,  Hiroshi Komorita ,  Noritaka Nakayama ,  Kiyoshi Iyogi

IPC: B32B704

CPC classification number: H05K1/0271 ,  C04B37/026 ,  C04B2235/786 ,  C04B2237/12 ,  C04B2237/121 ,  C04B2237/123 ,  C04B2237/127 ,  C04B2237/128 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/403 ,  C04B2237/405 ,  C04B2237/407 ,  C04B2237/408 ,  C04B2237/64 ,  C04B2237/704 ,  C04B2237/708 ,  C04B2237/72 ,  H01L23/13 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/38 ,  H05K3/4629 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2201/09745 ,  Y10T428/12028 ,  Y10T428/12069 ,  Y10T428/12201 ,  Y10T428/12396 ,  Y10T428/12528 ,  Y10T428/12576 ,  Y10T428/1259 ,  H01L2924/00

Abstract: The present invention provides a ceramic circuit board comprising: a ceramic substrate and a metal circuit plate bonded to the ceramic substrate through a brazing material layer; wherein the brazing material layer is composed of Al—Si group brazing material and an amount of Si contained in the brazing material is 7 wt % or less. In addition, it is preferable to form a thinned portion, holes, or grooves to outer peripheral portion of the metal circuit plate. According to the above structure of the present invention, there can be provided a ceramic circuit board having both high bonding strength and high heat-cycle resistance, and capable of increasing an operating reliability as electronic device.

Abstract translation: 本发明提供一种陶瓷电路板，包括：陶瓷基板和金属电路板，通过钎料层与陶瓷基板接合; 其特征在于，所述钎焊材料层由Al-Si基钎焊材料构成，所述钎料中含有的Si的量为7重量％以下。 此外，优选在金属电路板的外周部形成薄壁部，孔或槽。 根据本发明的上述结构，可以提供一种具有高接合强度和高耐热循环性的陶瓷电路板，能够提高作为电子设备的操作可靠性。

公开(公告)号：US06421253B1

公开(公告)日：2002-07-16

申请号：US09658398

申请日：2000-09-08

Applicant: Daniel Ray Ash, Jr.

Inventor： Daniel Ray Ash, Jr.

IPC: H05K704

CPC classification number: H05K1/021 ,  H05K1/0237 ,  H05K1/142 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/321 ,  H05K3/341 ,  H05K3/386 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/0191 ,  H05K2203/0405 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A delamination resistant electronics module assembly includes a printed circuit board layer coupled to a pallet via a cured epoxy preform. The preform may include conductive epoxy, or non-conductive epoxy with conductive traces. Component wells are collectively formed by the preform and PCB layer for placement of heat generating components, such as RF components. Methods of manufacturing module assemblies include curing the epoxy preform by applying a predetermined elevated pressure and heat to a sub-assembly of the pallet, preform layer, and PCB layer.

Abstract translation: 防分离电子模块组件包括通过固化环氧树脂预成型件连接到托盘的印刷电路板层。 预成型件可以包括导电环氧树脂或具有导电迹线的非导电环氧树脂。 组分井由预成型件和PCB层共同形成，用于放置诸如RF部件的发热部件。 制造模块组件的方法包括通过对托盘，预成型件层和PCB层的子组件施加预定的升高的压力和加热来固化环氧树脂预制件。

公开(公告)号：US06410978B1

公开(公告)日：2002-06-25

申请号：US09370990

申请日：1999-08-10

Applicant: Akio Yasukawa ,  Hirohisa Yamamura ,  Tatsuya Shigemura

Inventor： Akio Yasukawa ,  Hirohisa Yamamura ,  Tatsuya Shigemura

IPC: H01L2334

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09745 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device in which fatigue failure of a solder layer underneath a semiconductor chip mounted on a base can be prevented from occurring due to repetitions of turn-on and -off of power during operation thereof, is provided, that is, a recess is formed in the base in a part underneath the semiconductor chip so as to prevent occurrence of thermal expansion in the base.

Abstract translation: 提供了一种半导体装置，其中可以防止在其操作期间由于重复打开和关闭电源而发生安装在基座上的半导体芯片下方的焊料层的疲劳失效，即形成凹部 在半导体芯片下面的部分的基部中，以防止在基底中发生热膨胀。

公开(公告)号：US06365842B1

公开(公告)日：2002-04-02

申请号：US09679336

申请日：2000-10-04

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01R1204

CPC classification number: H01L24/83 ,  H01L24/16 ,  H01L24/28 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29499 ,  H01L2224/81141 ,  H01L2224/81903 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01R4/04 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.

Abstract translation: 本发明包括电互连，导电方法以及降低各向异性导电粘合剂内水平电导率的方法。 在一个实施例中，配置成电耦合第一衬底和第二衬底的电互连包括：具有阳构造的第一衬底的接合焊盘; 以及具有凹形结构的所述第二基板的接合焊盘，所述第二基板的接合焊盘被配置为在所述第一基板和所述第二基板的接合焊盘的电连接期间与所述第一基板的接合焊盘配合。 根据本发明的导电方法包括提供单独限定平面尺寸的第一和第二接合焊盘; 在具有大于所述平面尺寸的面积的表面积的界面处耦合所述第一和第二接合焊盘; 并且在耦合之后在第一和第二接合焊盘之间传导电力。

公开(公告)号：US06329609B1

公开(公告)日：2001-12-11

申请号：US09607098

申请日：2000-06-29

Applicant: Suryanarayana Kaja ,  Chandrika Prasad ,  RongQing Yu

Inventor： Suryanarayana Kaja ,  Chandrika Prasad ,  RongQing Yu

IPC: H01R909

CPC classification number: H01R12/62 ,  H01R12/58 ,  H05K1/0306 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/2036 ,  Y02P70/613

Abstract: An electronic component structure assembly comprising a thin film structure bonded to a multilayer ceramic substrate (MLC) using solder connections and wherein a non-conductive, compliant spacer preferably with a layer of thermoplastic adhesive on each surface thereof is interposed between the underlying MLC carrier and overlying thin film structure. The spacer includes a pattern of through-holes which corresponds to opposing contact pads of the thin film structure and MLC. The contact pads of at least one of the thin film structure or MLC have posts (e.g., metallic) thereon and the posts extend partly into the spacer through-holes whereby the height of the posts are greater than the thickness of the adhesive. The posts of the MLC have solder bumps thereon. After reflow under pressure the thin film structure is electrically and mechanically connected to the MLC and the join method has been found to provide a reliable and cost-effective process. The joined components also have enhanced operating life.

Abstract translation: 一种电子部件结构组件，其包括使用焊料连接而结合到多层陶瓷基板（MLC）的薄膜结构，并且其中优选地在其每个表面上具有热塑性粘合剂层的非导电柔性间隔件插入在下面的MLC载体和 上覆薄膜结构。 间隔件包括对应于薄膜结构和MLC的相对接触焊盘的通孔图案。 薄膜结构或MLC中的至少一个的接触垫在其上具有柱（例如金属），并且柱部分地延伸到间隔件通孔中，由此柱的高度大于粘合剂的厚度。 MLC的柱在其上具有焊料凸块。 在压力下回流之后，薄膜结构电气和机械地连接到MLC，并且已经发现连接方法提供可靠和成本有效的方法。 连接的部件也具有增强的使用寿命。

公开(公告)号：US06251766B1

公开(公告)日：2001-06-26

申请号：US09388755

申请日：1999-09-02

Applicant: Kishor V. Desai ,  Amit K. Sarkhel

Inventor： Kishor V. Desai ,  Amit K. Sarkhel

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract translation: 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

公开(公告)号：US06207550B1

公开(公告)日：2001-03-27

申请号：US09107319

申请日：1998-06-30

Applicant: Nobuhiro Hase ,  Minehiro Itagaki ,  Yoshifumi Nakamura ,  Satoru Yuhaku ,  Hiroaki Takezawa ,  Yoshihiro Bessho

Inventor： Nobuhiro Hase ,  Minehiro Itagaki ,  Yoshifumi Nakamura ,  Satoru Yuhaku ,  Hiroaki Takezawa ,  Yoshihiro Bessho

IPC: H01L2144

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/29 ,  H01L24/31 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15787 ,  H05K1/092 ,  H05K1/095 ,  H05K1/113 ,  H05K3/321 ,  H05K3/323 ,  H05K3/4007 ,  H05K3/4061 ,  H05K3/4069 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0278 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Disclosed is a method for mounting a semiconductor element, the method requiring no strict flatness for a substrate and being reliable in a semiconductor device produced by mounting a semiconductor element on a circuit substrate. In the multilayer circuit substrate comprising bump electrodes formed of a conductive paste, a conductive adhesive is applied to the top of bump electrodes and then leveled to obtain the end portions on the bump electrodes with a high coplanarity in height. The semiconductor element is mounted on this substrate using a combination of a conductive resin and a sealing resin or an anisotropic conductive sheet. Every top of the bump electrodes after the conductive adhesive is applied has a high coplanarity. The semiconductor element can be mounted with high reliability, on the substrate having such a poor flatness of the electrode face that mounting by a conventional method can not be applied.

Abstract translation: 公开了一种用于安装半导体元件的方法，该方法对于基板不需要严格的平坦度，并且在通过将半导体元件安装在电路基板上而制造的半导体器件中是可靠的。 在包含由导电浆料形成的凸块电极的多层电路基板中，将导电性粘合剂施加到凸块电极的顶部，然后平整，以在凸起电极上获得具有高共面度的端部。 半导体元件使用导电树脂和密封树脂或各向异性导电片的组合安装在该基板上。 使用导电性粘合剂之后的凸起电极的每个顶部具有高的共面性。 半导体元件可以以高可靠性安装在基板上，其电极面的平坦度差，不能施加常规方法的安装。

公开(公告)号：US06145365A

公开(公告)日：2000-11-14

申请号：US161807

申请日：1998-09-28

Applicant: Hideyuki Miyahara

Inventor： Hideyuki Miyahara

IPC: B21K21/00 ,  B21K21/14 ,  B23P15/00 ,  H01L21/48 ,  H01L23/36 ,  H05K3/04 ,  H05K3/44 ,  B21D28/02

CPC classification number: B21K23/00 ,  B21K21/00 ,  B21K21/14 ,  B23P15/00 ,  H01L21/4878 ,  H01L23/36 ,  H05K3/44 ,  H01L2924/0002 ,  H05K2201/0382 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K3/045

Abstract: An object of the present invention is to provide a method for forming a recess portion having an predetermined shape on one side of a metal plate without giving the metal plate any remarkable stress while forming the other side flat, which is suitable for a package for electronic parts such as an integrated circuit, etc. The method according to the present invention is characterized in that a recess portion having an predetermined shape is formed by plastically deforming a metal plate having a predetermined thickness by means of a press, etc. so as to form the recess portion having a depth smaller than the thickness on one side thereof and to form at the same time a protruding portion protruding on the other side of the metal plate. In the steps of plastically deforming the metal plate, metal corresponding to the recess portion is displaced to the protruding portion. Then, the protruding portion on the other side is removed by cutting processing to form the recess portion only on the one side of the metal plate and to form the other side flat.

Abstract translation: 本发明的目的是提供一种用于在金属板的一侧形成具有预定形状的凹部的方法，而不会在形成另一侧平面时给予金属板任何显着的应力，这适用于电子封装 根据本发明的方法，其特征在于，具有预定形状的凹部通过压机等使具有预定厚度的金属板进行塑性变形而形成，以便 形成具有比其一侧的厚度小的深度的凹部，并且同时形成在金属板的另一侧上突出的突出部。 在使金属板发生塑性变形的步骤中，与凹部对应的金属位移到突出部。 然后，通过切割处理去除另一侧的突出部分，仅在金属板的一侧上形成凹部并形成另一侧平面。

公开(公告)号：US6107877A

公开(公告)日：2000-08-22

申请号：US288906

申请日：1999-04-09

Applicant: Philip Miguelez ,  Rudolph Menna ,  Shutong Zhou ,  Timothy Cope

Inventor： Philip Miguelez ,  Rudolph Menna ,  Shutong Zhou ,  Timothy Cope

IPC: H03F1/32 ,  H03F1/52 ,  H05K1/02 ,  H05K3/00 ,  H03F1/00 ,  H03F1/26

CPC classification number: H03F1/523 ,  H03F1/3276 ,  H05K1/0253 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K3/0061

Abstract: An in-line distortion generator is coupled to an RF amplifier on a single PC board for producing an output signal of useful amplitude but with low composite triple beat and cross modulation distortions. The backplane under the section of the PC board upon which the distortion circuit resides is removed and the portion of the heat sink under the removed portion of the backplane is also removed. This eliminates any parasitic capacitances that could degrade the performance of the RF amplifier, thereby making the distortion circuit transparent to the RF amplifier. Furthermore, the layout of the predistortion circuitry has been specifically designed to enhance the performance of the circuitry without inducing any negative operating characteristics on the associated RF amplifier.

Abstract translation: 在线失真发生器耦合到单个PC板上的RF放大器，用于产生有用幅度的输出信号，但具有低复合三重拍摄和交叉调制失真。 去除了失真电路所在的PC板部分下的背板，并且除去背板拆卸部分下方的散热器部分。 这消除了可能降低RF放大器性能的任何寄生电容，从而使失真电路对RF放大器是透明的。 此外，预失真电路的布局已经被专门设计用于增强电路的性能，而不会在相关RF放大器上引起任何负的工作特性。