公开(公告)号：US10041166B2

公开(公告)日：2018-08-07

申请号：US15795768

申请日：2017-10-27

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/455 ,  H01L21/285 ,  H01L21/768

CPC classification number: C23C16/02 ,  C23C16/06 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76883

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US10032628B2

公开(公告)日：2018-07-24

申请号：US15144481

申请日：2016-05-02

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  David de Roest ,  Jacob Woodruff ,  Michael Eugene Givens ,  Jan Willem Maes ,  Timothee Blanquart

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/36 ,  H01L29/417

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/2254 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/41725

Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.

公开(公告)号：US09721786B2

公开(公告)日：2017-08-01

申请号：US14992942

申请日：2016-01-11

Applicant: ASM IP Holding B.V.

Inventor： Suvi P. Haukka ,  Fu Tang ,  Michael E. Givens ,  Jan Willem Maes ,  Qi Xie

IPC: H01L21/31 ,  H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L21/28 ,  H01L29/22 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02334 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02557 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28264 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

公开(公告)号：US09711350B2

公开(公告)日：2017-07-18

申请号：US14729510

申请日：2015-06-03

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Fu Tang ,  Michael Givens ,  Petri Raisanen ,  Jan Willem Maes

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/10 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02247 ,  H01L21/02112 ,  H01L21/02205 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/2807 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/518

Abstract: In some embodiments, a semiconductor surface having a high mobility semiconductor may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

公开(公告)号：US20170186754A1

公开(公告)日：2017-06-29

申请号：US15377439

申请日：2016-12-13

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Jan Willem Maes

IPC: H01L27/115 ,  H01L21/02

CPC classification number: H01L27/115 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02658 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00

Abstract: A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

公开(公告)号：US20170154806A1

公开(公告)日：2017-06-01

申请号：US15432263

申请日：2017-02-14

Applicant: ASM IP Holding B.V.

Inventor： Han Wang ,  Qi Xie ,  Delphine Longrie ,  Jan Willem Maes ,  David de Roest ,  Julian Hsieh ,  Chiyu Zhu ,  Timo Asikainen ,  Krzysztof Kachel ,  Harald Profijt

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/7685 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31122 ,  H01L21/31144 ,  H01L23/53266

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

公开(公告)号：US20170040164A1

公开(公告)日：2017-02-09

申请号：US14819274

申请日：2015-08-05

Applicant: ASM IP Holding B.V.

Inventor： Han Wang ,  Qi Xie ,  Delphine Longrie ,  Jan Willem Maes ,  David de Roest ,  Julian Hsieh ,  Chiyu Zhu ,  Timo Asikainen

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/283

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract translation: 提供了用于相对于同一衬底的第二电介质表面在衬底的第一导电表面上选择性地沉积含Al和N的材料的方法。 在一些方面，提供了形成用于集成电路制造中的含有Al和N的保护层或蚀刻停止层的方法。

公开(公告)号：US09553148B2

公开(公告)日：2017-01-24

申请号：US14678301

申请日：2015-04-03

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L51/05 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L21/768 ,  H01L21/288 ,  H01L29/423 ,  H01L29/78 ,  B82Y40/00

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。

公开(公告)号：US09520562B2

公开(公告)日：2016-12-13

申请号：US14334536

申请日：2014-07-17

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Jan Willem Maes ,  Tom Blomberg ,  Marko Tuominen ,  Suvi Haukka ,  Robin Roelofs ,  Jacob Woodruff

IPC: H01L45/00 ,  H01L21/02 ,  H01L27/24

CPC classification number: H01L45/1616 ,  H01L21/02175 ,  H01L21/0228 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1608

Abstract: The disclosed technology generally relates to semiconductor devices, and relates more particularly to resistive random access memory devices and methods of making the same. In one aspect, a method of forming a resistive random access memory cell of a random access memory device includes forming a first electrode and forming a resistive switching material comprising an oxide of a pnictogen element by atomic layer deposition. The method additionally includes forming a metallic layer comprising the pnictogen element by atomic layer deposition (ALD). The resistive switching material is interposed between the first electrode and the metallic layer.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及电阻随机存取存储器件及其制造方法。 一方面，一种形成随机存取存储器件的电阻随机存取存储单元的方法包括：通过原子层沉积形成第一电极并形成包含棱镜元件的氧化物的电阻开关材料。 该方法还包括通过原子层沉积（ALD）形成包含棱镜元件的金属层。 电阻开关材料介于第一电极和金属层之间。

公开(公告)号：US20160358835A1

公开(公告)日：2016-12-08

申请号：US15169430

申请日：2016-05-31

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Fu Tang ,  Michael Givens ,  Petri Raisanen ,  Jan Willem Maes ,  Xiaoqiang Jiang

IPC: H01L23/31 ,  H01L29/161 ,  H01L29/51 ,  C23C16/52 ,  H01L21/02 ,  C23C16/40 ,  C23C16/30 ,  C23C16/455 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L23/3171 ,  C23C16/0218 ,  C23C16/403 ,  C23C16/405 ,  H01L21/02112 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02304 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, native oxide is removed from the semiconductor surface and the surface is subsequently nitrided. In some other embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

Abstract translation: 在一些实施方案中，可以通过氮化，优选使用肼，肼衍生物或其组合来有效地钝化半导体表面。 该表面可以是晶体管沟道区的半导体表面。 在一些实施方案中，将天然氧化物从半导体表面上除去，随后将表面氮化。 在一些其它实施例中，在半导体表面形成半导体表面氧化物层，并且通过在表面形成半导体氮氧化物层来实现钝化，其中氮化对表面氧化物产生氮以形成氧氮化物层。 半导体氧化物层可以通过原子层沉积（ALD）沉积，并且氮化也可以作为ALD的一部分进行。