公开(公告)号：US20160104661A9

公开(公告)日：2016-04-14

申请号：US13913183

申请日：2013-06-07

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

摘要翻译： 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US09214419B2

公开(公告)日：2015-12-15

申请号：US14194502

申请日：2014-02-28

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC分类号： H01L21/44 ,  H01L23/495 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

摘要： A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

摘要翻译： 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US09087828B2

公开(公告)日：2015-07-21

申请号：US13797440

申请日：2013-03-12

申请人： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

发明人： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L23/495 ,  H01L21/58 ,  H01L23/00 ,  H01L23/433 ,  H01L23/492

CPC分类号： H01L23/49503 ,  H01L21/561 ,  H01L21/566 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/03

摘要： A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

摘要翻译： 具有厚底部金属的半导体器件包括在其前表面覆盖有顶部塑料封装层的半导体芯片和在其后表面处的背面金属层，顶部塑料封装层围绕金属凸块的侧壁与金属的顶表面 从顶部塑料封装层暴露的凸起，用于半导体芯片的芯片安装在其上以及塑料封装主体。

公开(公告)号：US09041172B1

公开(公告)日：2015-05-26

申请号：US14105473

申请日：2013-12-13

申请人： Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

发明人： Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/84 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

摘要翻译： 本发明一般涉及一种半导体器件，更具体地，涉及优化功率半导体器件的蠕变寿命距离及其制备方法。 功率半导体器件包括具有管芯焊盘的芯片安装单元和以等间距方式靠近管芯焊盘的一个侧边缘并排设置的多个引线，附接在管芯焊盘上的半导体芯片，以及 塑料包装体覆盖模片，半导体芯片，其中塑料包装体包括覆盖引线的引线肩部的至少一部分的塑料延伸部分，以在半导体器件的端子之间获得更好的电气安全距离，因此电压 设备的爬坡距离增加。

公开(公告)号：US20150136854A1

公开(公告)日：2015-05-21

申请号：US14396463

申请日：2012-05-08

申请人： Jun Lu ,  Young Liu ,  Xi Tao ,  Feng Chen ,  Ynjiun Paul Wang

发明人： Jun Lu ,  Young Liu ,  Xi Tao ,  Feng Chen ,  Ynjiun Paul Wang

IPC分类号： G06K7/10

CPC分类号： G06K7/10722 ,  G06K7/10009 ,  G06K7/10851 ,  G06K7/1413 ,  G06K19/06028 ,  H04N5/2251 ,  H04N5/23203 ,  H04N5/353 ,  H04N5/378

摘要： An encoded information reading (EIR) terminal can comprise a microprocessor communicatively coupled to a system bus, a memory, a communication interface, and a pluggable imaging assembly identified by a type identifier and configured to acquire an image comprising decodable indicia. The imaging assembly can comprise a two-dimensional image sensor configured to output an analog signal representative of the light reflected by an object located within the field of view of the imaging assembly. The EIR terminal can be configured to output, by processing the analog signal, the raw image data derived from the analog signal and/or a decoded message corresponding to the decodable indicia. The imaging assembly can be communicatively coupled to the system bus via an imaging assembly interface comprising a plurality of wires and a multi-pin connector. The imaging assembly inter face can comprise one or more wires configured to carry the imaging assembly type identifier. The EIR terminal can be configured, responsive to receiving the type identifier via the one or more wires, to retrieve from the memory one or more imaging assembly configuration information items corresponding to the type identifier and/or to receive via the communication interface one or more imaging assembly configuration information items corresponding to the type identifier. The EIR terminal can be further configured to control the imaging assembly using the imaging assembly configuration information items.

摘要翻译： 编码信息读取（EIR）终端可以包括通信地耦合到系统总线，存储器，通信接口和由类型标识符标识并被配置为获取包括可解码标记的图像的可插拔成像组件的微处理器。 成像组件可以包括被配置为输出表示由位于成像组件的视场内的物体反射的光的模拟信号的二维图像传感器。 EIR终端可以被配置为通过处理模拟信号来输出从模拟信号导出的原始图像数据和/或对应于可解码标记的解码消息。 成像组件可以经由包括多根电线和多针连接器的成像组件接口通信地耦合到系统总线。 成像组件界面可以包括一个或多个配置成承载成像组件类型标识符的线。 响应于经由一条或多条线路接收到类型标识符，可以配置EIR终端，以从存储器检索与该类型标识符相对应的一个或多个成像组件配置信息项和/或经由通信接口接收一个或多个 对应于类型标识符的成像组件配置信息项。 EIR终端还可以被配置成使用成像组件配置信息项来控制成像组件。

公开(公告)号：US09006870B2

公开(公告)日：2015-04-14

申请号：US13955206

申请日：2013-07-31

申请人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

发明人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

摘要翻译： 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20150040061A1

公开(公告)日：2015-02-05

申请号：US13997752

申请日：2012-08-24

申请人： Jun Lu ,  Yipeng Yang ,  Edwin L. Wang

发明人： Jun Lu ,  Yipeng Yang ,  Edwin L. Wang

IPC分类号： G06F3/0481 ,  G06F3/0484

CPC分类号： G06F3/0481 ,  G06F3/04842 ,  G06F3/1462 ,  G09G5/14 ,  G09G5/42 ,  G09G2370/022

摘要： A device, method and system of displaying a file on a mobile communication device may comprise duplicating at least a leftmost part of a file to obtain a duplicated leftmost part of the file, and displaying a frame through moving a display window along the frame, the frame comprising a rightmost part of the file and the duplicated leftmost part of the file, wherein the duplicated leftmost part of the file is placed on right of the rightmost part of the file. In some embodiments, the mobile communication device may control the display window to automatically move to a leftmost side of the frame, if the display window moves to a rightmost side of the frame, and further in response to a user instruction of continuing viewing the file.

摘要翻译： 在移动通信设备上显示文件的装置，方法和系统可以包括复制文件的至少最左部分以获得文件的最左边部分，并且通过沿着帧移动显示窗口来显示帧， 所述文件的最右边部分和所述文件的最左边部分是所述文件的最右边部分，所述文件的最左边部分位于所述文件的最右边部分的右侧。 在一些实施例中，如果显示窗口移动到帧的最右侧，则移动通信设备可以控制显示窗口自动移动到帧的最左侧，并且还响应于用户继续观看文件的指令 。

公开(公告)号：US08859508B2

公开(公告)日：2014-10-14

申请号：US12669653

申请日：2008-07-25

申请人： Jijun Chen ,  Lin Xu ,  Jun Zhou ,  Jun Lu ,  Rongrong Mao ,  Meng Tian ,  Qixin Zhou ,  Xuemei Zhang ,  Yong Shen ,  Zhiyong Jiang ,  Aixue Zuo

发明人： Jijun Chen ,  Lin Xu ,  Jun Zhou ,  Jun Lu ,  Rongrong Mao ,  Meng Tian ,  Qixin Zhou ,  Xuemei Zhang ,  Yong Shen ,  Zhiyong Jiang ,  Aixue Zuo

IPC分类号： A61K31/70 ,  A61K31/05 ,  A23L1/30 ,  A61K31/7032 ,  C07H15/203

CPC分类号： A23L1/30 ,  A23L33/10 ,  A23L33/105 ,  A61K31/05 ,  A61K31/7032 ,  C07H15/203

摘要： The present invention relates to the application of 5-methyl-1,3-benzenediol or its derivatives represented by Formula I; wherein the constituent variables are as defined herein or pharmaceutical compositions thereof containing them in the preparation of medicines or functional foods. The present studies indicate that 5-methyl-1,3-benzenediol or its derivatives represented by Formula I, wherein the constituent variables are as defined herein or pharmaceutical compositions thereof containing them show more significant antidepressant effects than fluoxetine or imipramine.

摘要翻译： 本发明涉及式I表示的5-甲基-1,3-苯二酚或其衍生物的应用; 其中组分变量如本文所定义，或其药物组合物含有它们在制备药物或功能性食品中。 本研究表明，式I表示的5-甲基-1,3-苯二酚或其衍生物，其中组分变量如本文所定义，或含有它们的药物组合物显示比氟西汀或丙咪嗪更显着的抗抑郁作用。

公开(公告)号：US20140264802A1

公开(公告)日：2014-09-18

申请号：US13797440

申请日：2013-03-12

申请人： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

发明人： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

IPC分类号： H01L23/495 ,  H01L21/58

CPC分类号： H01L23/49503 ,  H01L21/561 ,  H01L21/566 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/03

摘要： A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

摘要翻译： 具有厚底部金属的半导体器件包括在其前表面覆盖有顶部塑料封装层的半导体芯片和在其后表面处的背面金属层，顶部塑料封装层围绕金属凸块的侧壁与金属的顶表面 从顶部塑料封装层暴露的凸起，用于半导体芯片的芯片安装在其上以及塑料封装主体。

公开(公告)号：US08709893B2

公开(公告)日：2014-04-29

申请号：US13216122

申请日：2011-08-23

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8309 ,  H01L2224/83141 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

摘要翻译： 本发明涉及功率半导体器件及其制备方法。 特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。 通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。 与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。