公开(公告)号：US20110124207A1

公开(公告)日：2011-05-26

申请号：US12931518

申请日：2011-02-03

Applicant: James V. Russell

Inventor： James V. Russell

IPC: H01R12/00

CPC classification number: H01R13/2414 ,  H01R4/58 ,  H01R13/03 ,  H05K3/245 ,  H05K3/326 ,  H05K2201/0314 ,  H05K2201/10719

Abstract: An electrical connector using an isotropic conductive elastomer as the interconnect medium.

公开(公告)号：US20110085313A1

公开(公告)日：2011-04-14

申请号：US12579051

申请日：2009-10-14

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon. It further includes at least one wiring layer (V) designed to only electrically interconnect components on or within the second PCB, and at least one layer (X) designed to only electrically interconnect the components on the second PCB with the components on the first PCB. A first LGA interposer couples to the LGA disposed on the first surface of the first PCB, and electrically connects at least one component to the first PCB. A second LGA interposer is sandwiched between and couples to the LGA disposed on the second surface of the first PCB and to the LGA disposed on the first surface of the second PCB. It electrically connects the first PCB to components on the second PCB.

Abstract translation: 描述了用于在用作单个主板的共面板之间互连和分配信号和功率的系统，方法和主板组件。 主板组件包括具有相对的平行的第一和第二表面的多层第一印刷电路板，每个具有设置在其上的至少一个焊盘格栅阵列（LGA）。 组件还包括至少一个布线层（Y），其被设计成仅电连接第一PCB上或其内部的部件，以及至少一个布线层（X），其设计成仅将第一PCB上的部件电连接到多层第二PCB 。 所述多层第二PCB具有相对的平行的第一和第二表面，所述第一表面具有设置在其上的至少一个LGA。 它还包括至少一个被设计成仅电连接第二PCB上或第二PCB内的组件的布线层（V），以及设计成仅将第二PCB上的部件与第一PCB上的部件电互连的至少一个层（X） 。 第一LGA插入器耦合到布置在第一PCB的第一表面上的LGA，并且将至少一个部件电连接到第一PCB。 第二LGA插入件夹在布置在第一PCB的第二表面上的LGA之间并耦合到布置在第二PCB的第一表面上的LGA。 它将第一个PCB电连接到第二个PCB上的组件。

公开(公告)号：US20110085311A1

公开(公告)日：2011-04-14

申请号：US12631649

申请日：2009-12-04

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K1/111 ,  H01L23/64 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/181 ,  H05K3/301 ,  H05K3/341 ,  H05K2201/086 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/4902 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract translation: 公开了用于构造垂直配置的无源电子部件的制造技术。 电动无源部件构造成基本上垂直于包括第一平面的靶平台的结构，以提供更大的电极接触面积和更小的物理尺寸。 被构造为基本上垂直于与目标平台相关的平面的被动部件可以直接连接到集成电路或基板的焊盘触点，或者可以嵌入封装中以减少被动部件的面积开销，同时提高 被动元件在其应用中。

公开(公告)号：US07748991B2

公开(公告)日：2010-07-06

申请号：US11781018

申请日：2007-07-20

Applicant: Shinichi Nikaido ,  Haruo Miyazawa ,  Katsuya Yamagami

Inventor： Shinichi Nikaido ,  Haruo Miyazawa ,  Katsuya Yamagami

IPC: H01R12/00

CPC classification number: H05K7/1069 ,  H01R12/52 ,  H01R13/24 ,  H05K3/326 ,  H05K3/4092 ,  H05K3/42 ,  H05K2201/0367 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/10378 ,  H05K2201/10719

Abstract: An aspect of the present invention inheres in an IC socket includes a plate-like socket base body which includes through hole forming portions having a plurality of contact housing holes formed so as to penetrate the plate-like socket base in a front-to-back direction, and having through holes formed around the respective contact housing holes so as to penetrate the plate-like socket base in the front-to-back direction, and a plated layer formed continuously on an inner wall of the through hole, on the front and back surfaces of the through hole forming portion, and on a surface of the contact piece.

Abstract translation: 本发明的集成电路插座的一个方面包括一个板状插座底座本体，它包括通孔形成部分，该通孔形成部分具有多个接触容纳孔，该多个接触容纳孔形成为以前后方式穿过该板状插座底座 方向，并且具有围绕各个接触容纳孔形成的通孔，以便沿着前后方向穿透板状插座基座，以及在前面的通孔的内壁上连续形成的镀层 和通孔形成部分的后表面以及接触片的表面上。

公开(公告)号：US20100167466A1

公开(公告)日：2010-07-01

申请号：US12347800

申请日：2008-12-31

Applicant: Ravikumar Adimula ,  Myung Jin Yim

Inventor： Ravikumar Adimula ,  Myung Jin Yim

IPC: H01L21/98 ,  H05K7/00 ,  H05K3/34 ,  H05K3/30

CPC classification number: H05K3/323 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K2201/10719 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method for attaching the package substrate to a printed circuit board (PCB).

Abstract translation: 提出了一种制造具有金属凸块的封装衬底的装置和方法。 封装衬底包括衬底基底和形成在衬底基底上的多个金属凸块。 此后可以将微电子管芯附接到封装衬底。 还提出了一种将封装衬底附着到印刷电路板（PCB）的方法。

公开(公告)号：US07718216B2

公开(公告)日：2010-05-18

申请号：US11684739

申请日：2007-03-12

Applicant: Terry Lee Sterrett ,  Tian-An Chen ,  Saikumar Jayaraman

Inventor： Terry Lee Sterrett ,  Tian-An Chen ,  Saikumar Jayaraman

IPC: B05D5/12

CPC classification number: C08L101/12 ,  B29C39/026 ,  B29C70/58 ,  B29C70/882 ,  B29L2031/3406 ,  C08J5/10 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/31681 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.

Abstract translation: 公开了一种低温碰撞的方法。 提供能够在低温下通过自由基或阳离子聚合交联的树脂。 然后将导电颗粒加入到树脂中以形成混合物。 然后通过加热或暴露于光使混合物活化，以使混合物聚合。 在替代实施方案中，使用乙烯基醚树脂，其中加入导电颗粒。 混合物通过曝光聚合。

公开(公告)号：US07667320B2

公开(公告)日：2010-02-23

申请号：US12022254

申请日：2008-01-30

Applicant: Dustin P. Wood ,  Kaladhar Radhakrishnan

Inventor： Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC: H01L23/34

CPC classification number: H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract translation: 集成电路（IC）封装包括安装在基板的第一侧上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。

公开(公告)号：US07663232B2

公开(公告)日：2010-02-16

申请号：US11369571

申请日：2006-03-07

Applicant: Thomas H. Kinsley

Inventor： Thomas H. Kinsley

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L24/72 ,  H01L25/0652 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/325 ,  H05K2201/10598 ,  H05K2201/10719 ,  H01L2924/00

Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.

Abstract translation: 半导体器件组件包括诸如电子部件的元件和通过紧固件固定在一起的基板，该紧固件包括连续延伸穿过两个或更多个这样的元件中的孔的细长部分。 计算机系统包括这样的半导体器件组件。 用于将这些元件固定在一起的紧固件包括细长部分，第一端部件和第二端部件。 将多个半导体器件固定在一起的方法包括通过第一半导体器件中的孔和至少一个附加半导体器件中的孔插入紧固件的细长部分。 电路板包括与半导体器件组件中的孔阵列对应设置的多个孔。 每个孔的尺寸和构造被设计成接收用于维持半导体器件组件和电路板之间的组装关系的紧固件。

公开(公告)号：US20090310320A1

公开(公告)日：2009-12-17

申请号：US12214006

申请日：2008-06-16

Applicant: Weston Roth ,  Kevin Byrd ,  Damion Searls ,  James D. Jackson

Inventor： Weston Roth ,  Kevin Byrd ,  Damion Searls ,  James D. Jackson

IPC: H05K7/06 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10719 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A standoff contact array is disposed between a mounting substrate of a flip-chip package and a board. The standoff contact array is formable by mating a low-profile solder bump on the mounting substrate with a low-profile solder paste on the board. Thereafter, the standoff contact array is formed by reflowing the low-profile solder paste on the board against the low-profile solder bump on the mounting substrate.

Abstract translation: 间隔接触阵列设置在倒装芯片封装的安装基板和基板之间。 通过将安装基板上的低轮廓焊料凸块与板上的低轮廓焊膏配合，可以形成对位接触阵列。 此后，通过将板上的低轮廓焊膏回流到安装基板上的低轮廓焊料凸块上来形成间隔接触阵列。

公开(公告)号：US07628617B2

公开(公告)日：2009-12-08

申请号：US11525755

申请日：2006-09-22

Applicant: Dirk D. Brown ,  John D. Williams ,  William B. Long

Inventor： Dirk D. Brown ,  John D. Williams ,  William B. Long

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  H05K3/326 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0397 ,  H05K2201/10719 ,  H05K2201/10924 ,  H05K2201/10946

Abstract: An elastic contact array circuitized substrate includes a circuitized substrate provided with circuit traces, and an array of three dimensional contact elements joined to the circuitized substrate and electrically coupled to the circuit traces. In one configuration, the array of three dimensional contacts are formed in a spring sheet material having anisotropic grains whose long direction is selected with respect to the longitudinal direction of elastic contact arms, in accordance with desired properties. In another configuration of the invention, the circuit traces are formed integrally within the spring sheet material.

Abstract translation: 弹性接触阵列电路化衬底包括设置有电路迹线的电路化衬底和连接到电路化衬底并电耦合到电路迹线的三维接触元件的阵列。 在一种结构中，根据所需的性质，三维触点阵列形成为具有相对于弹性接触臂的纵向方向选择长方向的各向异性颗粒的弹簧片材料。 在本发明的另一种结构中，电路迹线一体形成在弹簧片材料内。