公开(公告)号：US08441092B2

公开(公告)日：2013-05-14

申请号：US12961229

申请日：2010-12-06

Applicant: Ravi Shankar ,  Olivier Le Neel

Inventor： Ravi Shankar ,  Olivier Le Neel

IPC: H01L31/058 ,  H01L23/34 ,  H01L21/00

CPC classification number: H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract translation: 半导体热电冷却器构造成通过冷却器的通道引导热量。 热电冷却器具有多个电极和位于电极的侧表面之间的第一介电材料。 与第一介电材料不同的第二介电材料与电极的顶表面接触。 第一电介质材料在电极的顶表面上方延伸，分离第二介电材料的部分，并与电极的顶表面的一部分接触。 第一电介质材料具有不同于第二电介质材料的热导率的导热系数。 可以选择与电极的顶表面接触的第一电介质材料与第二电介质材料的比例以控制保温。 半导体热电冷却器可以使用薄膜技术制造。

公开(公告)号：US20130105991A1

公开(公告)日：2013-05-02

申请号：US13312562

申请日：2011-12-06

Applicant: Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC: H01L23/488 ,  H01L21/60 ,  H01L21/50

CPC classification number: H01L24/97 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K1/186 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.

Abstract translation: 一种用于制造3D或PoP半导体封装的工艺包括在再构成的晶片上形成再分配层，然后激光钻出重建的晶片中的多个孔，从再构成的晶片的外表面延伸，以与第一再分配层 。 然后将焊球定位成与每个孔的开口相邻。 焊球熔化并允许填充孔，与相应的电迹线接触并形成多个焊料柱。 然后将重构的晶片的外表面平坦化，并且在平坦化表面上形成第二再分布层。 焊料柱用作通孔，将重新构成的晶片的相对侧上的第一和第二再分配层电耦合。

公开(公告)号：US20130105982A1

公开(公告)日：2013-05-02

申请号：US13287816

申请日：2011-11-02

Applicant: Yonggang Jin ,  Romain Coffy ,  Jerome Teysseyre

Inventor： Yonggang Jin ,  Romain Coffy ,  Jerome Teysseyre

IPC: H01L21/78 ,  H01L23/485

CPC classification number: H01L23/498 ,  H01L21/561 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/49124 ,  Y10T29/49174 ,  Y10T29/49204 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract translation: 扇出晶片级封装设置有嵌入重构晶片中的半导体管芯。 再分配层位于半导体管芯上方，并且在封装的表面上包括焊盘栅格阵列。 铜管散热器形成在芯片上的再分配层中，与多个配置成将半导体管芯的电路焊盘耦合到焊盘栅极阵列的接触焊盘的多个电迹线相同的层中。 在操作中，散热器提高了从模具到电路板的热传递的效率。

公开(公告)号：US20130100185A1

公开(公告)日：2013-04-25

申请号：US13281417

申请日：2011-10-25

Applicant: Jin Hao Chia ,  Yong Peng Yeo ,  Wei Leong Lim ,  Shi Min Veronica Goh ,  Mei Yu Muk

Inventor： Jin Hao Chia ,  Yong Peng Yeo ,  Wei Leong Lim ,  Shi Min Veronica Goh ,  Mei Yu Muk

IPC: B41J29/38 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/02071 ,  H01L21/32134 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76865

Abstract: A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second metal layer and patterned to form a mask. The second metal layer is etched. The mask is then removed and the first metal layer is patterned with the second metal layer acting as mask for the first metal layer.

Abstract translation: 在集成电路中形成金属互连的工艺包括在第一金属层上形成第一金属层和第二金属层。 将光刻胶放置在第二金属层上并图案化以形成掩模。 蚀刻第二金属层。 然后去除掩模，并且第一金属层被图案化，第二金属层用作第一金属层的掩模。

公开(公告)号：US20130069203A1

公开(公告)日：2013-03-21

申请号：US13237671

申请日：2011-09-20

Applicant: Janusz Karol Korycinski ,  Wanliang Wen

Inventor： Janusz Karol Korycinski ,  Wanliang Wen

IPC: H01L29/32 ,  H01L21/322

CPC classification number: H01L21/3226 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/78

Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.

Abstract translation: 提供了一种绝缘硅（SOI）晶圆。 在晶片的有源硅衬底上形成电介质层。 对电介质层进行图案化和蚀刻以暴露硅衬底的选定部分。 然后将杂质引入硅衬底的暴露部分中以用作吸杂区域。 然后去除电介质层，并在硅衬底上生长外延硅层。 通过吸气区域在硅的外延层中蚀刻沟槽，部分地去除吸气区域和其中包含的任何污染物。 吸附区域的剩余部分在后续工艺步骤中仍然作为吸气区域。

公开(公告)号：US20130062764A1

公开(公告)日：2013-03-14

申请号：US13232780

申请日：2011-09-14

Applicant: Yonggang Jin

Inventor： Yonggang Jin

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0384 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2784 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00

Abstract: A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.

Abstract translation: 形成在半导体衬底上的倒装芯片结构包括位于半导体衬底的前表面上的多个接触焊盘的直接与电接触的第一多个铜柱。 一层模塑料定位在基材的正面上，围绕并包围第一多个柱中的每一个并且具有与每个铜柱的前表面共面的前表面。 第二多个铜柱中的每一个位于第一多个铜柱之一的前表面上，并且焊料凸块位于每个第二多个柱的正面上。

公开(公告)号：US20130001740A1

公开(公告)日：2013-01-03

申请号：US13174591

申请日：2011-06-30

Applicant: Yiyi Ma

Inventor： Yiyi Ma

IPC: H01L27/02 ,  B32B23/02

CPC classification number: H01L23/3675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/19105 ,  Y10T428/24777 ,  H01L2924/00

Abstract: A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate.

Abstract translation: 散热器提供用于热增强倒装芯片球栅阵列封装。 在封装中，半导体管芯位于封装衬底的正前方，并通过焊球与其连接。 无源器件还可以与管芯一起耦合到衬底。 散热器位于衬底上并与模具热接触地模制。 散热器中心的突起通过热界面材料与模具的后表面接触，从模具中吸取热量以改善冷却。 该突起能够与较薄的模具紧密接触，同时容纳位于基板上的模具周围的较厚的无源器件。

公开(公告)号：US20120244664A1

公开(公告)日：2012-09-27

申请号：US13488276

申请日：2012-06-04

Applicant: Yonggang Jin ,  Xavier Baraton ,  Faxing Che

Inventor： Yonggang Jin ,  Xavier Baraton ,  Faxing Che

IPC: H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Abstract translation: 扇出晶片级封装包括具有顶表面，底表面，多个侧表面以及限定在顶表面上的接合焊盘的集成电路。 密封剂层基本上围绕集成电路的侧表面，密封剂层的高度基本上等于集成电路的高度。 凸块与集成电路间隔开，并且再分配层将集成电路的接合焊盘电耦合到凸块。

公开(公告)号：US20120171372A1

公开(公告)日：2012-07-05

申请号：US12982755

申请日：2010-12-30

Applicant: Hk Looi ,  Cheng-hai Cheh

Inventor： Hk Looi ,  Cheng-hai Cheh

IPC: B05D5/10 ,  B05C11/00 ,  B05C5/00

CPC classification number: B05B13/0431 ,  B05C5/0204 ,  B05C5/0225 ,  B05C5/0291 ,  B05C11/1039

Abstract: In automated gluing systems for semiconductor device manufacture, an automatic shutter system is provided for use with an adhesive dispenser that is configured to deposit adhesive for joining elements during final assembly processes. A shutter is configured to interpose itself between a needle tip of the dispenser and a working surface, on which devices in process are positioned, while the dispenser is in a ready position and not actually delivering adhesive, and to withdraw from the interposed position as, or immediately before the needle tip descends to a dispensing position to deposit adhesive on a device. In this way, drops of adhesive that fall from the needle tip while in the ready position are captured by the shutter and prevented from falling onto a device in process in an unintended location of the device.

Abstract translation: 在用于半导体器件制造的自动胶粘系统中，提供自动快门系统以与粘合剂分配器一起使用，其被配置为在最终组装过程期间沉积用于接合元件的粘合剂。 快门被配置为将自身插入到分配器的针尖和工作表面之间，在该工作表面处于正在处理的装置中，而分配器处于就绪位置，而不是实际输送粘合剂，并且从插入位置退出， 或者在针尖下降到分配位置之前，以将粘合剂沉积在装置上。 以这种方式，在就绪位置从针尖落下的粘合剂滴被快门捕获并防止在设备的非预期位置中落在正在处理的设备上。

公开(公告)号：US20120098104A1

公开(公告)日：2012-04-26

申请号：US12911171

申请日：2010-10-25

Applicant: Yonggang Jin

Inventor： Yonggang Jin

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/302

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/02 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/023 ,  H01L2924/00

Abstract: Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches.

Abstract translation: 这里描述的是在晶片处理期间形成用于由晶片形成的芯片的导电屏蔽层的技术。 在切割晶片之前，可以在芯片的多个侧面上形成导电屏蔽层，以将芯片与晶片分离。 可以处理晶片以形成基本上延伸穿过晶片的沟槽。 沟槽可以形成为相反的划线，其标识晶片的芯片之间的边界，并且可以延伸穿过晶片朝向划线。 可以沿着沟槽形成屏蔽层。