公开(公告)号：US20080026558A1

公开(公告)日：2008-01-31

申请号：US11889184

申请日：2007-08-09

Applicant: Soon Yoo ,  Dong Kwak ,  Hu Kim ,  Yong Kim ,  Dug Park ,  Yu Jung ,  Woo Lee

Inventor： Soon Yoo ,  Dong Kwak ,  Hu Kim ,  Yong Kim ,  Dug Park ,  Yu Jung ,  Woo Lee

IPC: H01L21/44

CPC classification number: H05K3/361 ,  G02F1/1345 ,  G02F1/13458 ,  H05K1/112 ,  H05K3/323 ,  H05K2201/0326 ,  H05K2201/09436 ,  H05K2201/09509

Abstract: A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side surfaces of the pad and a portion of the substrate adjacent to the side surfaces of the pad.

Abstract translation: 液晶显示器具有垫结构。 衬垫结构包括形成在衬底上的至少一个焊盘，形成在焊盘上的绝缘膜，以及通过穿过绝缘膜限定的接触孔连接到焊盘的至少一个导电层。 绝缘膜覆盖焊盘的侧表面和邻近焊盘侧表面的基板的一部分。

公开(公告)号：US20080024953A1

公开(公告)日：2008-01-31

申请号：US11495668

申请日：2006-07-31

Applicant: Hajime Sakamoto ,  Takashi Kariya ,  Yasuhiko Mano

Inventor： Hajime Sakamoto ,  Takashi Kariya ,  Yasuhiko Mano

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G2/06 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2203/171

Abstract: The capacitance of a capacitor is adjusted by forming openings in one of a pair of electrodes of the capacitor, the openings having different sizes d1, d2, d3, wherein d1>d2>d3> . . . and being arranged in numbers n1, n2, n3, . . . , respectively; and sequentially filling a necessary number of the openings with an electroconductive material in descending order of the size so as to adjust the capacitance gradually with an increasing degree of precision. The resulting capacitor is mounted to a printed wiring board.

Abstract translation: 通过在电容器的一对电极中的一个电极中形成开口来调节电容器的电容，开口具有不同的尺寸d 1，d 2，d 3，其中d 1> d 2> d 3>。 。 。 并且以n 1，n 2，n 3，...排列。 。 。 ， 分别; 并按照大小的降序顺序地用导电材料填充必要数量的开口，以随着精度的增加逐渐调整电容。 所得到的电容器安装到印刷线路板上。

公开(公告)号：US20080022519A1

公开(公告)日：2008-01-31

申请号：US11865794

申请日：2007-10-02

Applicant: Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

Inventor： Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

IPC: H05K3/36

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A laminating method. A structure that includes first and second dielectric layers respectively positioned on opposing surfaces of a thermally conductive layer is pressurized between 1000 and 3000 psi concurrent with being subjected to a thermal process, including the steps of: (a) heating the structure from ambient room temperature to a temperature between 670° F. to 695° F. in a heatup stage of duration 42 to 57 minutes; (b) after step (a), maintaining the structure at an approximately constant temperature between 670° F. and 695° F. in a dwell stage of duration 105 to 125 minutes; (c) after step (b), cooling the structure to 400° F. in a slow cool stage of duration of 120 to 150 minutes, wherein step (c) is performed after step (b); and (d) after step (3), cooling the structure to ambient room temperature in a rapid cool stage of duration less than 180 minutes.

Abstract translation: 层压方法。 包括分别位于导热层的相对表面上的第一和第二电介质层的结构在1000和3000psi之间被加压，同时进行热处理，包括以下步骤：（a）从环境室温 在持续时间为42至57分钟的加热阶段中温度在670°F至695°F之间; （b）在步骤（a）之后，在持续105至125分钟的停留阶段中，将结构保持在670°F和695°F之间的近似恒定温度; （c）在步骤（b）之后，在120至150分钟的缓慢冷却阶段中将结构冷却至400°F，其中步骤（c）在步骤（b）之后进行; 和（d）在步骤（3）之后，在持续时间小于180分钟的快速冷却阶段中将结构冷却至环境室温。

公开(公告)号：US07323762B2

公开(公告)日：2008-01-29

申请号：US10976878

申请日：2004-11-01

Applicant: Zao-Kuo Lai ,  Lin-Yin Wong

Inventor： Zao-Kuo Lai ,  Lin-Yin Wong

IPC: H01L29/00 ,  H01L27/102 ,  H01L27/082 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/095 ,  H05K1/167 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2203/1453 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract translation: 提出了一种具有嵌入式电阻器的半导体封装基板及其制造方法。 首先，在其上设置有第一电路层的内部电路板，并且在第一电路层中形成多个电阻电极。 然后，在内部电路板上形成图形化的电阻材料，并电连接到电阻器电极，以精确地限定电阻器的电阻值。 随后，在具有图案化电阻材料的电路板的表面上涂覆至少一个绝缘层。 至少一个图案化的第二电路层形成在绝缘层上，并且通过形成在绝缘层中的多个导电通孔或通过电路板形成的电镀通孔形成在电阻器电极上。

公开(公告)号：US20070297157A1

公开(公告)日：2007-12-27

申请号：US11474339

申请日：2006-06-26

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: a line that electrically connects either one of a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either one of the first lower electrode and the second lower electrode; and a line that electrically connects the other of the power pad and the ground pad to the other of the first upper electrode and the second upper electrode.

Abstract translation: 本发明提供一种具有内置电容器的布线板，其具有多层布线结构并且能够在其上安装IC芯片。 具有内置电容器的布线板包括：第一电容器，其内置在多层布线结构中，并且形成为使得设置在第一介电层的各个表面上的第一下电极和第一上电极之间的重叠区域是预定的 区; 以及第二电容器，其沿着与第一电介质层相同的平面内置在多层布线结构中，并且形成为使得第二下电极和第二上电极之间的重叠区域设置在具有该第二电介质层的第二电介质层的各个表面上 第一电介质层的厚度与预定面积不同。 所述布线基板还包括：将与所述IC芯片供电的功率垫中的任一个电连接的接线板和将所述IC芯片接地到所述第一下部电极和所述第二下部电极中的任一个的接地焊盘; 以及将所述电源焊盘和所述接地焊盘中的另一个电连接到所述第一上电极和所述第二上电极中的另一个的线。

公开(公告)号：US20070278000A1

公开(公告)日：2007-12-06

申请号：US11807425

申请日：2007-05-29

Applicant: Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

IPC: H05K1/16 ,  H05K7/00

CPC classification number: H05K1/186 ,  H05K1/023 ,  H05K1/0231 ,  H05K3/3442 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611

Abstract: According to one embodiment, a component-embedded printed wiring board includes a base including a component mounting surface, a pair of conductive patterns which is disposed on the component mounting surface of the base, and a circuit component which is mounted on the base so as to be in close contact with the component mounting surface between the conductive patterns and electrically connected to the conductive patterns.

Abstract translation: 根据一个实施例，组件嵌入式印刷线路板包括：基座，其包括部件安装表面;一对导电图案，设置在基座的部件安装表面上;电路部件，安装在基座上， 以与导电图案之间的部件安装表面紧密接触并且电连接到导电图案。

公开(公告)号：US20070271783A1

公开(公告)日：2007-11-29

申请号：US11832378

申请日：2007-08-01

Applicant: Tomoyuki IKEDA

Inventor： Tomoyuki IKEDA

IPC: H05K3/46

CPC classification number: H01L23/50 ,  B32B3/10 ,  B32B7/02 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09827 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer core board 10 includes tapered first via hole conductors 51 extending from the outer surface of a first insulating layer 24 to conductive portions 42a of a power source layer 42, second via hole conductors 52 extending from the outer surface of a second insulating layer 26 to the conductive portions 42a of the power source layer 42, tapered third via hole conductors 53 extending from the outer surface of the second insulating layer 26 to conductive portions 40a of a ground layer 40, and fourth via hole conductors 54 extending from the outer surface of a center insulating layer 22 to the conductive portions 40a of the ground layer 40. The first via hole conductors 51 are tapered, and thus the interval distance to the adjacent first via hole conductor 51 is shorter than straight-shaped first via hole conductors, and thus the pitch of the first via hole conductor 51 at the positive pole side and the fourth via hole conductor 54 at the negative pole side can be sufficiently reduced. This point is applicable to the third via hole conductors 53.

Abstract translation: 多层芯板10包括从第一绝缘层24的外表面延伸到电源层42的导电部分42a的锥形第一通孔导体51，从第二绝缘层的外表面延伸的第二通孔导体52 26连接到电源层42的导电部分42,4a，从第二绝缘层26的外表面延伸到接地层40的导电部分40a的锥形第三通孔导体53以及从第二绝缘层40延伸的第四通孔导体54 中心绝缘层22的外表面连接到接地层40的导电部分40a。 第一通孔导体51是锥形的，因此到相邻的第一通路孔导体51的间隔距离比直线状的第一通孔导体短，因此第一通孔导体51在正极侧的间距和 可以充分降低负极侧的第四通孔导体54。 这点适用于第三通孔导体53。

公开(公告)号：US20070266886A1

公开(公告)日：2007-11-22

申请号：US11736495

申请日：2007-04-17

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: C09D5/00

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US07282648B2

公开(公告)日：2007-10-16

申请号：US11356524

申请日：2006-02-16

Applicant: Han Kim ,  Chang Myung Ryu ,  Young Jae Lee

Inventor： Han Kim ,  Chang Myung Ryu ,  Young Jae Lee

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K2201/091 ,  H05K2201/09309 ,  H05K2201/09509 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention relates to a capacitor-embedded PCB and a method of manufacturing the same. The capacitor-embedded PCB includes a dielectric layer, a lower electrode layer formed under the dielectric layer, and an upper electrode layer formed on the dielectric layer and configured to have at least one first blind via hole that is inwardly formed.

Abstract translation: 本发明涉及电容器嵌入式PCB及其制造方法。 电容器嵌入式PCB包括电介质层，在电介质层下形成的下电极层和形成在电介质层上的上电极层，并且被配置为具有至少一个向内形成的第一盲通孔。

公开(公告)号：US20070230146A1

公开(公告)日：2007-10-04

申请号：US11728546

申请日：2007-03-26

Applicant: Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

IPC: H05K7/00

CPC classification number: H05K1/186 ,  H05K1/0271 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611

Abstract: According to one embodiment, a printed-wiring board with a built-in component includes a first base material including a component mounting surface. A circuit component is mounted on the component mounting surface of the first base material. A stress relaxation material covers the circuit component. A second base material is stacked on the first base material by interposing, between the first base material and the second base material, an insulating layer covering the stress relaxation material.

Abstract translation: 根据一个实施例，具有内置部件的印刷电路板包括包括部件安装表面的第一基材。 电路部件安装在第一基材的部件安装表面上。 应力松弛材料覆盖电路部件。 第二基材通过在第一基材和第二基材之间插入覆盖应力松弛材料的绝缘层而堆叠在第一基材上。