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    Generating multiple secure hashes from a single data buffer
    174.
    发明授权
    Generating multiple secure hashes from a single data buffer 有权

    公开(公告)号：US09917689B2

    公开(公告)日：2018-03-13

    申请号：US15231595

    申请日：2016-08-08

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Vinodh Gopal ,  Wajdi K. Feghali ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

    IPC: H04L9/06 ,  G06F21/72 ,  H04L9/32

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

    Method and apparatus for efficiently executing hash operations
    176.
    发明授权
    Method and apparatus for efficiently executing hash operations 有权

    公开(公告)号：US09912481B2

    公开(公告)日：2018-03-06

    申请号：US14228056

    申请日：2014-03-27

    Applicant: INTEL CORPORATION

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/32 ,  G06F12/08 ,  G06F12/0811 ,  H04L9/06

    CPC classification number: H04L9/3239 ,  G06F9/30007 ,  G06F12/0811 ,  G06F2212/283 ,  H04L9/0643 ,  H04L2209/125

    Abstract: An apparatus and method are described for executing hash functions on a processor. For example, one embodiment of a processor comprises: a register set including a first storage location and a second storage location in which state variables for a hash function are to be stored; an execution unit to execute the hash function and to initially designate the first storage location as storing a first set of state values used for computing rounds of the hash function, and to initially designate a second storage location as storing a second set of state values also used for computing the rounds of the hash function; and the execution unit to execute a plurality of rounds of the hash function using the first and second sets of state data, wherein executing includes swapping the designations of the first storage location and second storage location such that the first storage location is designated to store the first set of state values for a first set of rounds and the second set of state values for a second set of rounds, and wherein the second storage location is designated to store the second set of state values for the first set of rounds and the first set of state values for the second set of rounds.

    SECURE ELLIPTIC CURVE CRYPTOGRAPHY INSTRUCTIONS
    177.
    发明申请
    SECURE ELLIPTIC CURVE CRYPTOGRAPHY INSTRUCTIONS 审中-公开

    公开(公告)号：US20180062843A1

    公开(公告)日：2018-03-01

    申请号：US15248643

    申请日：2016-08-26

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal

    IPC: H04L9/30 ,  G06F21/72 ,  G06F7/72

    CPC classification number: H04L9/3066 ,  G06F7/725 ,  G06F21/72 ,  H04L2209/12 ,  H04L2209/16

    Abstract: A processor of an aspect includes a decode unit to decode an elliptic curve cryptography (ECC) point-multiplication with obfuscated input information instruction. The ECC point-multiplication with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for an ECC point-multiplication operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the ECC point-multiplication with obfuscated input information instruction, is to store an ECC point-multiplication result in a destination storage location that is to be indicated by the ECC point-multiplication with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

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