公开(公告)号：US08828848B2

公开(公告)日：2014-09-09

申请号：US13328746

申请日：2011-12-16

Applicant: Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.

Abstract translation: 提供具有沿侧壁的凸缘的模具和形成模具的方法。 还提供了一种包装模具的方法。 通过形成具有第一宽度的第一凹口，然后在第一凹口内形成第二凹槽，使得第二凹槽具有小于第一宽度的第二宽度，来切割诸如经处理晶片的基底。 第二凹口延伸穿过衬底，从而切割衬底。 第一宽度和第二宽度之间的宽度差导致沿着骰子的侧壁的凸缘。 骰子可以放置在基底上，例如插入物，以及放置在骰子和基底之间的底部填充物。 凸缘防止或减少底部填充物在相邻骰子之间的距离。 可以在基材上形成模塑料。

公开(公告)号：US08698308B2

公开(公告)日：2014-04-15

申请号：US13362913

申请日：2012-01-31

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L29/40

CPC classification number: H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a α ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract translation: 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将粘合凸块结构中的铜柱的总高度除以接合的凸块结构的间隙来限定的α比来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。

公开(公告)号：US08653658B2

公开(公告)日：2014-02-18

申请号：US13308162

申请日：2011-11-30

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.

Abstract translation: 用于形成凸块结构的机构减少了芯片和封装衬底之间的间隙的变化。 通过在电镀后对芯片和/或基板上的凸块结构上的焊料层进行平坦化，可以控制凸块结构的高度，以最小化晶片内部以及晶片位置，图案密度，晶粒尺寸和工艺变化中的变化。 结果，芯片和基板之间的间隔被控制得更均匀。 因此，底部填充质量得到改善。

公开(公告)号：US08643148B2

公开(公告)日：2014-02-04

申请号：US13397204

申请日：2012-02-15

Applicant: Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

Inventor： Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

IPC: H01L21/78

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Abstract translation: 包装部件包括基板，其中基板具有前表面和在前表面上的后表面。 通孔穿过基底。 导电特征设置在衬底的背表面上并电连接到通孔。 第一电介质图案形成导电特征的环覆盖边缘部分。 底部金属（UBM）被布置在导电特征的中心部分上并与其接触。 聚合物接触衬底的侧壁。 将第二电介质图案设置在聚合物上并对准聚合物。 第一和第二电介质图案由相同的电介质材料形成，并且设置在基本上相同的水平。

公开(公告)号：US20130244346A1

公开(公告)日：2013-09-19

申请号：US13420383

申请日：2012-03-14

Applicant: Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

Inventor： Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

IPC: H01L21/66 ,  G06F17/00

CPC classification number: G06F17/00 ,  H01L22/12 ,  H01L22/20 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

Abstract translation: 公开了包装方法，材料分配方法和装置以及自动测量系统。 在一个实施例中，包装半导体器件的方法包括将第二管芯耦合到第一管芯的顶表面，在第一管芯和第二管芯之间分配第一量的底部填充材料，以及捕获底部填充材料的图像。 基于所捕获的图像，在第一模具和第二模具之间分配第二量或不需要额外量的底部填充材料。

公开(公告)号：US20130233601A1

公开(公告)日：2013-09-12

申请号：US13412958

申请日：2012-03-06

Applicant: Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

Inventor： Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

Abstract translation: 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性微片和由用于接收电测试探针的第二金属形成的电测试焊盘，并电连接到所述一个或多个功能性微波。 表面金属布线结构还包括多个由第一金属形成的牺牲片，其电连接到电测试焊盘，其中牺牲微片比一个或多个功能性微片更靠近电测试垫定位。

公开(公告)号：US20130203215A1

公开(公告)日：2013-08-08

申请号：US13369083

申请日：2012-02-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L21/56

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/11 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

公开(公告)号：US08500182B2

公开(公告)日：2013-08-06

申请号：US12818022

申请日：2010-06-17

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: B25J15/00

CPC classification number: H01L21/67346 ,  H01L21/6838 ,  H01L21/68785

Abstract: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

Abstract translation: 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。

公开(公告)号：US20130187258A1

公开(公告)日：2013-07-25

申请号：US13356173

申请日：2012-01-23

Applicant: Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

Inventor： Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L27/06 ,  H01L21/78

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract translation: 一种方法包括将第一和第二包装部件接合在第三包装部件的顶表面上，并分配聚合物。 聚合物包括在第一和第三包装部件之间的空间中的第一部分，在第二和第三包装部件之间的空间中的第二部分和第一和第二包装部件之间的间隙中的第三部分。 然后在聚合物上进行固化步骤。 在固化步骤之后，将聚合物的第三部分锯切以在第一和第二包装部件之间形成沟槽。

公开(公告)号：US08455995B2

公开(公告)日：2013-06-04

申请号：US12762085

申请日：2010-04-16

Applicant: Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/04

CPC classification number: H01L23/3121 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

Abstract translation: 一种器件包括具有顶表面和底表面的衬底的插入器。 多个穿通基板通孔（TSV）穿过基板。 多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。 互连结构形成在衬底的顶表面上并电耦合到多个TSV。