公开(公告)号：US20180174825A1

公开(公告)日：2018-06-21

申请号：US15890117

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Melitta Manyin HON ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02057 ,  H01L29/66636 ,  H01L29/66795

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US20180166288A1

公开(公告)日：2018-06-14

申请号：US15832571

申请日：2017-12-05

Applicant: Applied Materials, Inc.

Inventor： Hua CHUNG ,  Matthias BAUER ,  Schubert S. CHU ,  Satheesh KUPPURAO

IPC: H01L21/285 ,  H01L29/167 ,  H01L29/45

CPC classification number: H01L21/28518 ,  H01L21/02043 ,  H01L21/02532 ,  H01L21/285 ,  H01L21/32053 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.

公开(公告)号：US20170194430A1

公开(公告)日：2017-07-06

申请号：US15395928

申请日：2016-12-30

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Michael G. WARD ,  Shiyu SUN ,  Michael CHUDZIK ,  Nam Sung KIM ,  Hua CHUNG ,  Yi-Chiau HUANG ,  Chentsau YING ,  Ying ZHANG ,  Chi-Nung NI ,  Lin DONG ,  Dongqing YANG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/764 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

公开(公告)号：US20160013273A1

公开(公告)日：2016-01-14

申请号：US14673033

申请日：2015-03-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US20150371868A1

公开(公告)日：2015-12-24

申请号：US14320597

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/311 ,  H01L29/10 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes in a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer includes a coating layer coated on an outer surface of a main body formed in the material layer, selectively removing a first portion of the coating layer from the material layers to expose the underlying main body of the material layers while maintaining a second portion of the coating layer remaining on the material layers, laterally etching the main body of the material layers exposed by removal of the coating layer, and selectively growing film layers on the exposed main body of the material layer.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实例中，在衬底上形成纳米线结构的方法包括在衬底上的悬浮的纳米线结构中，悬浮的纳米线包括在悬浮的纳米线结构中重复形成间隔关系的多个材料层，其中材料层包括涂层 层涂覆在形成在材料层中的主体的外表面上，从材料层选择性地去除涂层的第一部分，以暴露材料层的下面的主体，同时保持涂层的第二部分保持在 材料层，横向蚀刻通过去除涂层而暴露的材料层的主体，以及选择性地在材料层的暴露的主体上生长膜层。

公开(公告)号：US20140130739A1

公开(公告)日：2014-05-15

申请号：US14149560

申请日：2014-01-07

Applicant: Applied Materials, Inc.

Inventor： Barry L. CHIN ,  Alfred W. MAK ,  Lawrence C. LEI ,  Ming XI ,  Hua CHUNG ,  Ken Kaung LAI ,  Jeong Soo BYUN

IPC: C23C16/455

CPC classification number: C23C16/45544 ,  C23C16/45525 ,  C23C16/45548 ,  C23C16/45551 ,  C23C16/4583

Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.

Abstract translation: 描述了用于原子层沉积（ALD）的方法和装置。 在一个实施例中，一种装置包括具有连续的内部容积的真空室主体，其包括与第二沉积区域间隔开的第一沉积区域，所述室主体具有可操作以最小化第一和第二沉积物之间的气体混合的特征 区域，形成在所述室主体中并且定位成优先地将气体脉冲至所述第一沉积区域的第一气体端口，以使得能够在所述第一沉积区域中执行第一沉积工艺，以及形成在所述室主体中并定位成 优选提供脉冲气体到第二沉积区域以使得能够在第二沉积区域中进行第二沉积工艺。

公开(公告)号：US20140116470A1

公开(公告)日：2014-05-01

申请号：US14149526

申请日：2014-01-07

Applicant: Applied Materials, Inc.

Inventor： Jie SU ,  Lori D. WASHINGTON ,  Sandeep NIJHAWAN ,  Olga KRYLIOUK ,  Jacob GRAYSON ,  Sang Won KANG ,  Dong Hyung LEE ,  Hua CHUNG

IPC: C23C16/44

CPC classification number: C23C16/4405 ,  C23C16/4404 ,  C23C16/45574 ,  H01L21/67115

Abstract: A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.

Abstract translation: 一种用于从处理室的内表面去除沉积产物并用于防止或减缓这种沉积产物的生长的方法和装置。 将含卤素气体提供到室以蚀刻掉沉积产物。 将卤素清除气体提供到室以除去任何残留的卤素。 卤素清除气体通常通过暴露于电磁能（通过热能在处理室内）或通过电场，UV或微波在远程室中而被激活。 可以将沉积前体添加到卤素清除气体中，以在室的内表面上形成耐沉积膜。 另外，或者也可以通过在PVD工艺中将耐沉积金属溅射到处理室的内部部件上来形成耐沉积膜。

公开(公告)号：US20190301011A1

公开(公告)日：2019-10-03

申请号：US16366570

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Prerna Sonthalia GORADIA ,  Robert Jan VISSER ,  Abhishek DUBE ,  Flora Fong-Song CHANG ,  Hua CHUNG

IPC: C23C16/44 ,  C23C16/52 ,  C23C16/48

Abstract: Embodiments of the disclosure may provide a method and apparatus for cleaning an epi-chamber at a low temperature so that residues are quickly eliminated from a surface of the epi-chamber after a performing a low temperature epitaxial deposition process. Some of the benefits of the present disclosure include flowing a chlorine containing gas to an improved epi-chamber having UV capability to chlorinate and quickly remove the epitaxial deposition residues at a low cleaning process temperature. As such, residues are decreased or removed from the epi-chamber such that further processing may be performed.

公开(公告)号：US20190172728A1

公开(公告)日：2019-06-06

申请号：US16172266

申请日：2018-10-26

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/673

Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

公开(公告)号：US20190169767A1

公开(公告)日：2019-06-06

申请号：US16266646

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: C30B25/08 ,  C30B35/00 ,  C30B29/40 ,  H01L21/67 ,  C30B25/16 ,  C30B25/00 ,  C23C16/48 ,  C23C16/56 ,  C30B33/00 ,  C23C16/30 ,  C30B25/10 ,  C30B25/12 ,  C30B25/14

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.