公开(公告)号：US20120007211A1

公开(公告)日：2012-01-12

申请号：US12830547

申请日：2010-07-06

Applicant: Aleksandar Aleksov ,  Arnab Sarkar ,  Henning Braunisch ,  Jerry R. Bautista

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Henning Braunisch ,  Jerry R. Bautista

IPC: H01L27/10 ,  H01L21/50

CPC classification number: H01L21/78 ,  H01L22/32 ,  H01L23/52 ,  H01L23/585 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present disclosure relates to the field of microelectronic die packaging, particularly multi-chip packaging, wherein on-substrate modularity is enabled by using in-street die-to-die interconnects to facilitate signal routing between microelectronic dice. These in-street die-to-die interconnects may allow for manufacturing of several products on a single microelectronic substrate, which may lead to improved microelectronic die and/or microelectronic module harvesting and increased product yields.

Abstract translation: 本公开内容涉及微电子管芯封装领域，特别是多芯片封装，其中通过使用街道芯片间管芯互连以实现微电子管芯之间的信号路由，能够实现基板上的模块化。 这些在街头的模 - 芯互连可以允许在单个微电子衬底上制造几个产品，这可以导致改进的微电子管芯和/或微电子模块收获和增加的产品产量。

公开(公告)号：US20110302771A1

公开(公告)日：2011-12-15

申请号：US13215458

申请日：2011-08-23

Applicant: Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

Inventor： Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

IPC: H01F41/14

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01F17/062 ,  H01F41/16 ,  H01F2017/0073 ,  H01L23/498 ,  H01L23/50 ,  H01L23/645 ,  H01L2224/13

Abstract: A method of manufacturing an inductor for a microelectronic device comprises providing a substrate (610), forming a first plurality of inductor windings (111, 211, 411, 620, 2030) over the substrate, forming a magnetic inductor core (112, 212, 412, 810) over the first plurality of inductor windings, and forming a second plurality of inductor windings (113, 213, 413, 1010) over the magnetic inductor core. In another embodiment, the method comprises forming the inductor on a sacrificial substrate (1610) such that the inductor can subsequently be mounted onto a carrier tape (1810). In yet another embodiment, a method of manufacturing a substrate for a microelectronic device comprises forming an inductor within a build-up layer (101, 102, 103, 104) of a substrate.

Abstract translation: 制造用于微电子器件的电感器的方法包括提供衬底（610），在衬底上形成第一组多个电感器绕组（111,211,411,620,2030），形成磁感应芯（112,212， 在第一组多个电感器绕组上方形成第二多个电感器绕组（113,213,413,1010），并在磁感应器芯上形成第二多个电感器绕组（113,213,413,1010）。 在另一个实施例中，该方法包括在牺牲衬底（1610）上形成电感器，使得电感器可以随后安装在载带（1810）上。 在另一个实施例中，制造微电子器件的衬底的方法包括在衬底的堆积层（101,102,103,104）内形成电感器。

公开(公告)号：US20090309687A1

公开(公告)日：2009-12-17

申请号：US12157803

申请日：2008-06-11

Applicant: Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

Inventor： Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

IPC: H01F5/00 ,  H01F41/00 ,  H01F41/14

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01F17/062 ,  H01F41/16 ,  H01F2017/0073 ,  H01L23/498 ,  H01L23/50 ,  H01L23/645 ,  H01L2224/13

Abstract: A method of manufacturing an inductor for a microelectronic device comprises providing a substrate (610), forming a first plurality of inductor windings (111, 211, 411, 620, 2030) over the substrate, forming a magnetic inductor core (112, 212, 412, 810) over the first plurality of inductor windings, and forming a second plurality of inductor windings (113, 213, 413, 1010) over the magnetic inductor core. In another embodiment, the method comprises forming the inductor on a sacrificial substrate (1610) such that the inductor can subsequently be mounted onto a carrier tape (1810). In yet another embodiment, a method of manufacturing a substrate for a microelectronic device comprises forming an inductor within a build-up layer (101, 102, 103, 104) of a substrate.

Abstract translation: 制造用于微电子器件的电感器的方法包括提供衬底（610），在衬底上形成第一组多个电感器绕组（111,211,411,620,2030），形成磁感应芯（112,212， 在第一组多个电感器绕组上方形成第二多个电感器绕组（113,213,413,1010），并在磁感应器芯上形成第二多个电感器绕组（113,213,413,1010）。 在另一个实施例中，该方法包括在牺牲衬底（1610）上形成电感器，使得电感器可以随后安装在载带（1810）上。 在另一个实施例中，制造微电子器件的衬底的方法包括在衬底的堆积层（101,102,103,104）内形成电感器。

公开(公告)号：US20080237718A1

公开(公告)日：2008-10-02

申请号：US11694626

申请日：2007-03-30

Applicant: Vladimir Noveski ,  Sujit Sharan ,  Aleksandar Aleksov

Inventor： Vladimir Noveski ,  Sujit Sharan ,  Aleksandar Aleksov

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first HOD layer on a first side of a first silicon substrate, forming a CMOS region on a second side of the silicon substrate, forming amorphous silicon on the CMOS region, recrystallizing the amorphous silicon to form a first single crystal silicon layer, and forming a second HOD layer on the first single crystal silicon layer.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在第一硅衬底的第一侧上形成第一HOD层，在硅衬底的第二侧上形成CMOS区域，在CMOS区域上形成非晶硅，使非晶硅重结晶以形成第一单晶 硅层，并在第一单晶硅层上形成第二HOD层。

公开(公告)号：US20180084643A1

公开(公告)日：2018-03-22

申请号：US15267872

申请日：2016-09-16

Applicant: Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Adel A. Elsherbini ,  Sasha Oster ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan

Inventor： Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Adel A. Elsherbini ,  Sasha Oster ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/147 ,  A61B5/00 ,  A61B5/6833 ,  A61B2562/164 ,  A61B2562/166 ,  H05K1/0283 ,  H05K1/112 ,  H05K1/181 ,  H05K3/365 ,  H05K2201/10151 ,  H05K2201/10265 ,  H05K2201/10303 ,  H05K2201/10318

Abstract: A circuit interconnect may be used in biometric data sensing and feedback applications. A circuit interconnect may be used in device device-to-device connections (e.g., Internet of Things (IoT) devices), including applications that require connection between stretchable and rigid substrates. A circuit interconnect may include a multi-pin, snap-fit attachment mechanism, where the attachment mechanism provides an electrical interconnection between a rigid substrate and a flexible or stretchable substrate. The combination of a circuit interconnect and flexible or stretchable substrate provides improved electrical connection reliability, allows for greater stretchability and flexibility of the circuit traces, and allows for more options in connecting a stretchable circuit trace to a rigid PCB.

公开(公告)号：US20170094749A1

公开(公告)日：2017-03-30

申请号：US14866625

申请日：2015-09-25

Applicant: Adel Elsherbini ,  Sasha Oster ,  Nadine L. Dabby ,  Aleksandar Aleksov ,  Braxton Lathrop ,  Feras Eid

Inventor： Adel Elsherbini ,  Sasha Oster ,  Nadine L. Dabby ,  Aleksandar Aleksov ,  Braxton Lathrop ,  Feras Eid

IPC: H05B33/28 ,  A42B1/00 ,  A41D1/00 ,  F21V33/00 ,  H05B33/06 ,  A41B1/08 ,  H05B33/04

CPC classification number: H05B33/28 ,  A41B1/08 ,  A41D1/002 ,  A42B1/004 ,  A42B1/242 ,  F21V33/0008 ,  H05B33/04 ,  H05B33/06

Abstract: Some forms relate to a stretchable computing display device. The stretchable computing display device includes a stretchable base; a patterned conductive section mounted on the stretchable base, wherein the patterned conductive section includes a first portion and a second portion that is electrically isolated from the first portion; an electroluminescent material mounted on the stretchable base such that the electroluminescent material is between the first portion and the second portion of the patterned conductive section; an encapsulant that covers at least a portion of the patterned conductive section; and a textile such that the stretchable base is mounted on the textile, wherein the textile is part of a garment.

公开(公告)号：US20170093007A1

公开(公告)日：2017-03-30

申请号：US14866693

申请日：2015-09-25

Applicant: Adel A. ELSHERBINI ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

Inventor： Adel A. ELSHERBINI ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H01P3/026 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US09257276B2

公开(公告)日：2016-02-09

申请号：US13977663

申请日：2011-12-31

Applicant: Aleksandar Aleksov ,  Tony Dambrauskas ,  Danish Faruqui ,  Mark S. Hlad ,  Edward R. Prack

Inventor： Aleksandar Aleksov ,  Tony Dambrauskas ,  Danish Faruqui ,  Mark S. Hlad ,  Edward R. Prack

IPC: H01L23/488 ,  H01L21/02 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

Abstract translation: 描述了电子组件及其制造。 一个实施例涉及一种方法，包括在半导体晶片上的金属凸块上沉积有机薄膜层，该有机薄膜层也形成在与晶片上的金属凸块相邻的表面上。 将晶片切割成多个半导体管芯结构，该管芯结构包括有机薄膜层。 半导体管芯结构附着到基板上，其中，附接包括在管芯结构上的金属凸块和衬底上的焊盘之间形成焊料接合，并且其中焊料接合延伸穿过有机薄膜层。 然后将有机薄膜层暴露于等离子体。 描述和要求保护其他实施例。

公开(公告)号：US09233835B2

公开(公告)日：2016-01-12

申请号：US13992791

申请日：2011-12-06

Applicant: Aleksandar Aleksov ,  Sanka Ganesan

Inventor： Aleksandar Aleksov ,  Sanka Ganesan

IPC: H05K7/10 ,  B81B7/00 ,  B23K35/02 ,  H01L23/498 ,  H05K3/34 ,  H01L23/00

CPC classification number: B81B7/0006 ,  B23K35/0288 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

Abstract translation: 本说明书涉及制造微电子组件的领域，其中微电子器件可以附接到具有多个成形和取向的焊点的微电子衬底。 成形和定向的焊接接头可以是基本上椭圆形的，其中基本上椭圆形焊点的长轴可以基本上朝向微电子器件的中性点或中心定向。 成形和取向的焊接接头的实施例可以减少由于应力（例如来自微电子器件和微电子衬底之间的热膨胀应力）引起的焊点故障的可能性。

公开(公告)号：US20120261838A1

公开(公告)日：2012-10-18

申请号：US13531827

申请日：2012-06-25

Applicant: Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L25/07 ,  H01L21/60 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract translation: 多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120） ）和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140） 。 基板的任何部分都不在桥下。 该桥在第一管芯和第二管芯之间形成连接。 或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。 该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。