公开(公告)号：US09252080B1

公开(公告)日：2016-02-02

申请号：US14514640

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L21/24 ,  H01L23/48 ,  H01L21/768 ,  H01L21/321

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract translation: 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US20160027744A1

公开(公告)日：2016-01-28

申请号：US14876889

申请日：2015-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03

Abstract: A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 一种方法，包括在导电焊盘上方和金属结构之上形成第一电介质层，导电焊盘和金属结构各自位于衬底上方的互连层内，在第一介电层中形成第一开口和第二开口， 所述第一开口与所述导电焊盘对准并且暴露所述导电焊盘，并且所述第二开口与所述金属结构对准并且暴露所述金属结构，并且在所述导电焊盘上，所述金属结构上以及所述第一介电层上方形成金属衬垫。 该方法还可以包括在金属衬垫之上形成第二电介质层，以及在第二电介质层之上形成第三电介质层，第三电介质层比第一电介质层或第二电介质层厚。

公开(公告)号：US10163673B2

公开(公告)日：2018-12-25

申请号：US14047237

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Kenneth F. McAvey, Jr. ,  Charles F. Musante ,  Anthony K. Stamper

IPC: H01L21/673 ,  H01L21/683

Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly, a method of temporarily bonding a semiconductor wafer to a wafer carrier with a multi-layered contact layer as well as a structure. A method is disclosed that includes: forming a first layer on a surface of a semiconductor wafer; forming a second layer on the first layer; bonding a perforated carrier to the second layer; and removing the semiconductor wafer from the perforated carrier. The first layer may be composed of an adhesive. The second layer may be composed of a material having a higher outgassing temperature than the first layer.

公开(公告)号：US20170148754A1

公开(公告)日：2017-05-25

申请号：US15421737

申请日：2017-02-01

Applicant: GlobalFoundries Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US09633962B2

公开(公告)日：2017-04-25

申请号：US14048483

申请日：2013-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L21/7684 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

公开(公告)号：US20170069518A1

公开(公告)日：2017-03-09

申请号：US14845896

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brett Cucci ,  Thai Doan ,  Jeffrey P. Gambino ,  Rebecca K. Kelley ,  Jed H. Rankin ,  Daniel S. Vanslette

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/68757 ,  H01L21/76898

Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.

Abstract translation: 蚀刻装置和方法。 该装置包括具有顶表面的支撑衬底; 从支撑基板的顶表面上的最下层到距离支撑基板最远的最上层，形成在支撑基板的顶表面上的多个层的堆叠; 并且其中最顶层的顶表面的整体不是平面的，并且不是最上层的多个层中的至少一个是导电层。

公开(公告)号：US09543219B2

公开(公告)日：2017-01-10

申请号：US14557819

申请日：2014-12-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Mark J. Esposito ,  Jeffrey P. Gambino ,  Prakash Periasamy

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L22/10 ,  H01L21/67248 ,  H01L21/768 ,  H01L22/30 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of monitoring a temperature of a plurality of regions in a substrate during a deposition process, the monitoring of the temperature including: forming, in the monitored plurality of regions, a plurality of metal structures each with a different metal pattern density, where each metal pattern density corresponds to a threshold temperature at or above which metal voids and surface roughness are formed in the plurality of metal structures, and detecting metal voids and surface roughness in the plurality of metal structures to determine the temperature of the monitored plurality of regions.

Abstract translation: 一种在沉积过程中监测衬底中的多个区域的温度的方法，所述温度的监测包括：在所监视的多个区域中形成多个金属结构，每个金属结构具有不同的金属图案密度，其中每个 金属图案密度对应于多个金属结构中形成金属空隙和表面粗糙度的阈值温度，并且检测多个金属结构中的金属空隙和表面粗糙度，以确定被监测的多个区域的温度。

公开(公告)号：US09466547B1

公开(公告)日：2016-10-11

申请号：US14734600

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

CPC classification number: H01L23/3171 ,  H01L21/4853 ,  H01L21/563 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/03

Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

Abstract translation: 在集成电路（IC）芯片钝化层内形成一种形貌结构。 形貌结构包括在钝化层的顶表面下方延伸的沟槽，并且在与IC芯片的最上面布线相关联的钝化层下面的最上面的金属间介电层的顶表面之上。 形貌结构还可以包括沿着沟槽的周边的钝化层的顶表面上方的脊。 形状结构可以位于一系列IC芯片接触焊盘之间和/或可以位于特定的IC芯片接触焊盘周围。 形貌结构增加了钝化层的表面积，从而增加了与钝化层的底部填充结合。 地形结构还影响毛细管底部填充物的毛细管运动，并且可以定位成加速，减慢或转移毛细管底部填充物的移动。

公开(公告)号：US10446421B2

公开(公告)日：2019-10-15

申请号：US15951547

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  John M. Cohn ,  Jeffrey P. Gambino ,  William J. Murphy ,  Anthony J. Telensky

IPC: H01L21/67 ,  C23C14/54 ,  G01B7/06 ,  G03F7/20 ,  G05B19/418

Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

公开(公告)号：US10409006B2

公开(公告)日：2019-09-10

申请号：US15874210

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Charles L. Arvin ,  Robert Leidy

IPC: G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  G02B6/124 ,  G02B6/13 ,  G02B6/36

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.